ad9081_fmca_ebz/vck190: Updated to hierarchical versal transceiver
Vivado cannot nest multiple block designs than two layers. This makes replication of designs difficult. Create a hierarchy around the Versal transceiver that includes also the converters, this type of interface would match the util_adxcvr interface. Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>main
Laszlo Nagy
Laszlo Nagy
parent
7e5a638386
commit
731ed0a7a5
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@ -135,7 +135,7 @@ if {$ADI_PHY_SEL == 1} {
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} else {
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source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl
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create_bd_cell -type container -reference jesd_phy jesd204_phy
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create_versal_phy jesd204_phy $TX_NUM_OF_LANES
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create_bd_port -dir I gt_reset
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@ -291,40 +291,22 @@ if {$ADI_PHY_SEL == 1} {
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ad_xcvrcon util_mxfe_xcvr axi_mxfe_tx_xcvr axi_mxfe_tx_jesd {} {} tx_device_clk
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} else {
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make_bd_intf_pins_external [get_bd_intf_pins jesd204_phy/gt_bridge_ip_0_diff_gt_ref_clock]
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ad_connect ref_clk_q0 jesd204_phy/GT_REFCLK
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set rx_link_clock jesd204_phy/rxusrclk_gt_bridge_ip_0
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set tx_link_clock jesd204_phy/txusrclk_gt_bridge_ip_0
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set rx_link_clock jesd204_phy/rxusrclk_out
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set tx_link_clock jesd204_phy/txusrclk_out
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# Connect PHY to Link Layer
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for {set j 0} {$j < $RX_NUM_OF_LANES} {incr j} {
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ad_ip_instance jesd204_versal_gt_adapter_tx tx_adapt_${j}
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ad_connect axi_mxfe_tx_jesd/tx_phy${j} tx_adapt_${j}/TX
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ad_connect tx_adapt_${j}/txdata jesd204_phy/ch${j}_txdata_ext
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ad_connect tx_adapt_${j}/txheader jesd204_phy/ch${j}_txheader_ext
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ad_connect axi_mxfe_tx_jesd/tx_phy${j} jesd204_phy/tx${j}
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ad_ip_instance jesd204_versal_gt_adapter_rx rx_adapt_${j}
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ad_connect axi_mxfe_rx_jesd/rx_phy${j} rx_adapt_${j}/RX
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ad_connect rx_adapt_${j}/rxdata jesd204_phy/ch${j}_rxdata_ext
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ad_connect rx_adapt_${j}/rxheader jesd204_phy/ch${j}_rxheader_ext
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ad_connect rx_adapt_${j}/rxheadervalid jesd204_phy/ch${j}_rxheadervalid_ext
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ad_connect rx_adapt_${j}/rxgearboxslip jesd204_phy/ch${j}_rxgearboxslip_ext
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ad_connect axi_mxfe_rx_jesd/rx_phy${j} jesd204_phy/rx${j}
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# link clock to adapter
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ad_connect $rx_link_clock rx_adapt_${j}/usr_clk
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ad_connect $tx_link_clock tx_adapt_${j}/usr_clk
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}
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ad_connect $sys_cpu_clk jesd204_phy/apb3clk_quad
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ad_connect $sys_cpu_clk jesd204_phy/apb3clk_gt_bridge_ip_0
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ad_connect $sys_cpu_clk jesd204_phy/apb3clk
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ad_connect GND jesd204_phy/rate_sel_gt_bridge_ip_0
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ad_connect GND jesd204_phy/reset_rx_pll_and_datapath_in
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ad_connect GND jesd204_phy/reset_tx_pll_and_datapath_in
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ad_connect gt_reset jesd204_phy/gt_reset_gt_bridge_ip_0
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ad_connect gt_reset jesd204_phy/gtreset_in
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ad_connect axi_mxfe_rx_jesd/rx_axi/device_reset jesd204_phy/reset_rx_datapath_in
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ad_connect axi_mxfe_tx_jesd/tx_axi/device_reset jesd204_phy/reset_tx_datapath_in
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@ -513,3 +495,4 @@ if {$TDD_SUPPORT} {
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ad_connect GND $dac_data_offload_name/sync_ext
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ad_connect GND $adc_data_offload_name/sync_ext
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}
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@ -1,22 +1,43 @@
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set top_design [current_bd_design]
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# TODO: This works only up to 4 lanes on 64B66B
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proc create_versal_phy {
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{ip_name versal_phy}
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{num_lanes 2}
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{lane_rate 11.88}
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{ref_clock 360}
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} {
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create_bd_design "jesd_phy"
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set num_quads [expr round(1.0*$num_lanes/4)]
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set progdiv_clock [format %.3f [expr $lane_rate * 1000 / 66]]
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create_bd_cell -type ip -vlnv xilinx.com:ip:gt_bridge_ip:1.1 gt_bridge_ip_0
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create_bd_cell -type hier ${ip_name}
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# Common interface
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create_bd_pin -dir O ${ip_name}/rxusrclk_out -type clk
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create_bd_pin -dir O ${ip_name}/txusrclk_out -type clk
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create_bd_pin -dir I ${ip_name}/GT_REFCLK -type clk
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create_bd_pin -dir I ${ip_name}/apb3clk -type clk
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create_bd_pin -dir I ${ip_name}/gtreset_in
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create_bd_pin -dir I ${ip_name}/reset_rx_datapath_in
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create_bd_pin -dir I ${ip_name}/reset_tx_datapath_in
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ad_ip_instance gt_bridge_ip ${ip_name}/gt_bridge_ip_0
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set_property -dict [list \
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CONFIG.BYPASS_MODE {true} \
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CONFIG.IP_NO_OF_LANES ${num_lanes} \
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CONFIG.IP_PRESET {GTY-JESD204_64B66B} \
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CONFIG.IP_LR0_SETTINGS { \
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CONFIG.IP_LR0_SETTINGS [list \
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PRESET GTY-JESD204_64B66B \
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INTERNAL_PRESET JESD204_64B66B \
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GT_TYPE GTY \
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GT_DIRECTION DUPLEX \
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TX_LINE_RATE 11.88 \
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TX_LINE_RATE $lane_rate \
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TX_PLL_TYPE LCPLL \
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TX_REFCLK_FREQUENCY 360 \
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TX_ACTUAL_REFCLK_FREQUENCY 360.000000000000 \
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TX_REFCLK_FREQUENCY $ref_clock \
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TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \
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TX_FRACN_ENABLED true \
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TX_FRACN_NUMERATOR 0 \
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TX_REFCLK_SOURCE R0 \
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@ -29,16 +50,16 @@ set_property -dict [list \
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TX_OUTCLK_SOURCE TXPROGDIVCLK \
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TXPROGDIV_FREQ_ENABLE true \
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TXPROGDIV_FREQ_SOURCE LCPLL \
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TXPROGDIV_FREQ_VAL 180.000 \
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TXPROGDIV_FREQ_VAL $progdiv_clock \
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TX_DIFF_SWING_EMPH_MODE CUSTOM \
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TX_64B66B_SCRAMBLER false \
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TX_64B66B_ENCODER false \
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TX_64B66B_CRC false \
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TX_RATE_GROUP A \
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RX_LINE_RATE 11.88 \
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RX_LINE_RATE $lane_rate \
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RX_PLL_TYPE LCPLL \
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RX_REFCLK_FREQUENCY 360 \
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RX_ACTUAL_REFCLK_FREQUENCY 360.000000000000 \
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RX_REFCLK_FREQUENCY $ref_clock \
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RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \
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RX_FRACN_ENABLED true \
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RX_FRACN_NUMERATOR 0 \
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RX_REFCLK_SOURCE R0 \
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@ -49,7 +70,7 @@ set_property -dict [list \
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RX_OUTCLK_SOURCE RXPROGDIVCLK \
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RXPROGDIV_FREQ_ENABLE true \
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RXPROGDIV_FREQ_SOURCE LCPLL \
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RXPROGDIV_FREQ_VAL 180.000 \
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RXPROGDIV_FREQ_VAL $progdiv_clock \
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INS_LOSS_NYQ 12 \
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RX_EQ_MODE LPM \
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RX_COUPLING AC \
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@ -160,15 +181,79 @@ set_property -dict [list \
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RESET_SEQUENCE_INTERVAL 0 \
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RX_COMMA_PRESET NONE \
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RX_COMMA_VALID_ONLY 0 \
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} \
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] [get_bd_cells gt_bridge_ip_0]
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] \
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] [get_bd_cells ${ip_name}/gt_bridge_ip_0]
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apply_bd_automation -rule xilinx.com:bd_rule:gt_ips -config { DataPath_Interface_Connection {Auto} Lane0_selection {NULL} Lane10_selection {NULL} Lane11_selection {NULL} Lane12_selection {NULL} Lane13_selection {NULL} Lane14_selection {NULL} Lane15_selection {NULL} Lane16_selection {NULL} Lane17_selection {NULL} Lane18_selection {NULL} Lane19_selection {NULL} Lane1_selection {NULL} Lane2_selection {NULL} Lane3_selection {NULL} Lane4_selection {NULL} Lane5_selection {NULL} Lane6_selection {NULL} Lane7_selection {NULL} Lane8_selection {NULL} Lane9_selection {NULL} Quad0_selection {NULL} Quad10_selection {NULL} Quad11_selection {NULL} Quad12_selection {NULL} Quad13_selection {NULL} Quad14_selection {NULL} Quad15_selection {NULL} Quad16_selection {NULL} Quad17_selection {NULL} Quad18_selection {NULL} Quad19_selection {NULL} Quad1_selection {NULL} Quad2_selection {NULL} Quad3_selection {NULL} Quad4_selection {NULL} Quad5_selection {NULL} Quad6_selection {NULL} Quad7_selection {NULL} Quad8_selection {NULL} Quad9_selection {NULL}} [get_bd_cells gt_bridge_ip_0]
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ad_ip_instance gt_quad_base ${ip_name}/gt_quad_base_0
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 ${ip_name}/GT_Serial
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ad_connect ${ip_name}/gt_quad_base_0/GT_Serial ${ip_name}/GT_Serial
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validate_bd_design
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ad_ip_instance bufg_gt ${ip_name}/bufg_gt_rx
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ad_ip_instance bufg_gt ${ip_name}/bufg_gt_tx
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save_bd_design
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close_bd_design [current_bd_design]
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ad_connect ${ip_name}/gt_quad_base_0/ch0_rxoutclk ${ip_name}/bufg_gt_rx/outclk
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ad_connect ${ip_name}/gt_quad_base_0/ch0_txoutclk ${ip_name}/bufg_gt_tx/outclk
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current_bd_design [get_bd_designs $top_design]
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ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/gt_bridge_ip_0/gt_rxusrclk
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ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/gt_bridge_ip_0/gt_txusrclk
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ad_connect ${ip_name}/gt_bridge_ip_0/rxusrclk_out ${ip_name}/rxusrclk_out
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ad_connect ${ip_name}/gt_bridge_ip_0/txusrclk_out ${ip_name}/txusrclk_out
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for {set j 0} {$j < $num_lanes} {incr j} {
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ad_ip_instance jesd204_versal_gt_adapter_tx ${ip_name}/tx_adapt_${j}
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ad_connect ${ip_name}/tx_adapt_${j}/TX_GT_IP_Interface ${ip_name}/gt_bridge_ip_0/GT_TX${j}_EXT
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# TODO: This works only up to 4 lanes
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ad_connect ${ip_name}/gt_bridge_ip_0/GT_TX${j} ${ip_name}/gt_quad_base_0/TX${j}_GT_IP_Interface
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 ${ip_name}/tx${j}
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ad_connect ${ip_name}/tx${j} ${ip_name}/tx_adapt_${j}/TX
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ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/tx_adapt_${j}/usr_clk
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}
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for {set j 0} {$j < $num_lanes} {incr j} {
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ad_ip_instance jesd204_versal_gt_adapter_rx ${ip_name}/rx_adapt_${j}
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ad_connect ${ip_name}/rx_adapt_${j}/RX_GT_IP_Interface ${ip_name}/gt_bridge_ip_0/GT_RX${j}_EXT
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# TODO: This works only up to 4 lanes
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ad_connect ${ip_name}/gt_bridge_ip_0/GT_RX${j} ${ip_name}/gt_quad_base_0/RX${j}_GT_IP_Interface
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create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 ${ip_name}/rx${j}
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ad_connect ${ip_name}/rx${j} ${ip_name}/rx_adapt_${j}/RX
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ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/rx_adapt_${j}/usr_clk
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}
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for {set i 0} {$i < $num_quads} {incr i} {
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for {set j 0} {$j < 4} {incr j} {
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ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/gt_quad_base_${i}/ch${j}_rxusrclk
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ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/gt_quad_base_${i}/ch${j}_txusrclk
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}
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}
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# Clocks and resets
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ad_connect ${ip_name}/apb3clk ${ip_name}/gt_bridge_ip_0/apb3clk
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ad_connect ${ip_name}/gtreset_in ${ip_name}/gt_bridge_ip_0/gtreset_in
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ad_connect ${ip_name}/reset_rx_datapath_in ${ip_name}/gt_bridge_ip_0/reset_rx_datapath_in
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ad_connect ${ip_name}/reset_tx_datapath_in ${ip_name}/gt_bridge_ip_0/reset_tx_datapath_in
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ad_ip_instance xlconcat ${ip_name}/xlconcat_0 [list \
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NUM_PORTS $num_quads \
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]
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ad_ip_instance util_reduced_logic ${ip_name}/util_reduced_logic_0 [list \
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C_SIZE $num_quads \
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]
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for {set j 0} {$j < $num_quads} {incr j} {
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ad_connect ${ip_name}/xlconcat_0/In${j} ${ip_name}/gt_quad_base_${j}/gtpowergood
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ad_connect ${ip_name}/apb3clk ${ip_name}/gt_quad_base_${j}/apb3clk
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ad_connect ${ip_name}/GT_REFCLK ${ip_name}/gt_quad_base_${j}/GT_REFCLK0
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}
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ad_connect ${ip_name}/xlconcat_0/dout ${ip_name}/util_reduced_logic_0/Op1
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ad_connect ${ip_name}/util_reduced_logic_0/Res ${ip_name}/gt_bridge_ip_0/gtpowergood
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}
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@ -127,6 +127,12 @@ module system_top #(
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wire rx_device_clk;
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// instantiations
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IBUFDS_GTE5 i_ibufds_ref_clk (
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.CEB (1'd0),
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.I (fpga_refclk_in_p),
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.IB (fpga_refclk_in_n),
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.O (ref_clk),
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.ODIV2 ());
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IBUFDS i_ibufds_sysref (
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.I (sysref2_p),
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@ -269,8 +275,8 @@ module system_top #(
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.GT_Serial_0_grx_p (rx_data_p_loc[3:0]),
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.GT_Serial_0_grx_n (rx_data_n_loc[3:0]),
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.gt_bridge_ip_0_diff_gt_ref_clock_0_clk_p(fpga_refclk_in_p),
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.gt_bridge_ip_0_diff_gt_ref_clock_0_clk_n(fpga_refclk_in_n),
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.ref_clk_q0 (ref_clk),
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.ref_clk_q1 (ref_clk),
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.rx_device_clk (rx_device_clk),
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.tx_device_clk (tx_device_clk),
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