From 7376218e014e996d0bd1cd445bb92cf5fc518e29 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Fri, 3 Jul 2015 17:46:45 +0300 Subject: [PATCH] axi_spdif_rx: Initial commit NOT tested. --- library/axi_spdif_rx/axi_spdif_rx.vhd | 438 +++++++++++++++++++ library/axi_spdif_rx/axi_spdif_rx_constr.xdc | 0 library/axi_spdif_rx/axi_spdif_rx_ip.tcl | 52 +++ library/axi_spdif_rx/rx_cap_reg.vhd | 176 ++++++++ library/axi_spdif_rx/rx_decode.vhd | 265 +++++++++++ library/axi_spdif_rx/rx_package.vhd | 248 +++++++++++ library/axi_spdif_rx/rx_phase_det.vhd | 398 +++++++++++++++++ library/axi_spdif_rx/rx_status_reg.vhd | 150 +++++++ 8 files changed, 1727 insertions(+) create mode 100644 library/axi_spdif_rx/axi_spdif_rx.vhd create mode 100644 library/axi_spdif_rx/axi_spdif_rx_constr.xdc create mode 100644 library/axi_spdif_rx/axi_spdif_rx_ip.tcl create mode 100644 library/axi_spdif_rx/rx_cap_reg.vhd create mode 100644 library/axi_spdif_rx/rx_decode.vhd create mode 100644 library/axi_spdif_rx/rx_package.vhd create mode 100644 library/axi_spdif_rx/rx_phase_det.vhd create mode 100644 library/axi_spdif_rx/rx_status_reg.vhd diff --git a/library/axi_spdif_rx/axi_spdif_rx.vhd b/library/axi_spdif_rx/axi_spdif_rx.vhd new file mode 100644 index 000000000..0149410fc --- /dev/null +++ b/library/axi_spdif_rx/axi_spdif_rx.vhd @@ -0,0 +1,438 @@ +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- Copyright 2011-2013(c) Analog Devices, Inc. +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- - Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- - Redistributions in binary form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in +-- the documentation and/or other materials provided with the +-- distribution. +-- - Neither the name of Analog Devices, Inc. nor the names of its +-- contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- - The use of this software may or may not infringe the patent rights +-- of one or more patent holders. This license does not release you +-- from the requirement that you obtain separate licenses from these +-- patent holders to use this software. +-- - Use of the software either in source or binary form, must be run +-- on or directly connected to an Analog Devices Inc. component. +-- +-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. +-- +-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- istvan.csomortani@analog.com (c) Analog Devices Inc. +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library work; +use work.rx_package.all; +use work.axi_ctrlif; +use work.axi_streaming_dma_rx_fifo; +use work.pl330_dma_fifo; + +entity axi_spdif_rx is + generic + ( + C_S_AXI_DATA_WIDTH : integer := 32; + C_S_AXI_ADDR_WIDTH : integer := 32; + C_DMA_TYPE : integer := 0 + ); + port + ( + --SPDIF ports + rx_int_o : out std_logic; + spdif_rx_i : in std_logic; + spdif_rx_i_osc : out std_logic; + + --AXI Lite inter face + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_RREADY : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_AWREADY : out std_logic; + + --AXI STREAM interface + M_AXIS_ACLK : in std_logic; + M_AXIS_TREADY : in std_logic; + M_AXIS_TDATA : out std_logic_vector(31 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TVALID : out std_logic; + M_AXIS_TKEEP : out std_logic_vector(3 downto 0); + + --PL330 DMA interface + DMA_REQ_ACLK : in std_logic; + DMA_REQ_RSTN : in std_logic; + DMA_REQ_DAVALID : in std_logic; + DMA_REQ_DATYPE : in std_logic_vector(1 downto 0); + DMA_REQ_DAREADY : out std_logic; + DMA_REQ_DRVALID : out std_logic; + DMA_REQ_DRTYPE : out std_logic_vector(1 downto 0); + DMA_REQ_DRLAST : out std_logic; + DMA_REQ_DRREADY : in std_logic + ); +end entity axi_spdif_rx; + +------------------------------------------------------------------------------ +-- Architecture section +------------------------------------------------------------------------------ + +architecture IMP of axi_spdif_rx is + + signal wr_data : std_logic_vector(31 downto 0); + signal rd_data : std_logic_vector(31 downto 0); + signal wr_addr : integer range 0 to 3; + signal rd_addr : integer range 0 to 3; + signal wr_stb : std_logic; + signal rd_ack : std_logic; + + signal version_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal control_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal chstatus_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + + signal sampled_data : std_logic_vector(31 downto 0); + + signal sample_ack : std_logic; + signal sample_din : std_logic_vector(31 downto 0); + signal sample_wr : std_logic; + + signal conf_rxen : std_logic; + signal conf_sample : std_logic; + signal evt_en : std_logic; + signal conf_chas : std_logic; + signal conf_valid : std_logic; + signal conf_blken : std_logic; + signal conf_valen : std_logic; + signal conf_useren : std_logic; + signal conf_staten : std_logic; + signal conf_paren : std_logic; + signal config_rd : std_logic; + signal config_wr : std_logic; + + signal conf_mode : std_logic_vector(3 downto 0); + signal conf_bits : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0); + signal conf_dout : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0); + + signal fifo_data_out : std_logic_vector(31 downto 0); + signal fifo_data_ack : std_logic; + signal fifo_reset : std_logic; + signal tx_fifo_stb : std_logic; + + signal enable : boolean; + + signal lock : std_logic; + + signal rx_data : std_logic; + signal rx_data_en : std_logic; + signal rx_block_start : std_logic; + signal rx_channel_a : std_logic; + signal rx_error : std_logic; + signal lock_evt : std_logic; + signal ud_a_en : std_logic; + signal ud_b_en : std_logic; + signal cs_a_en : std_logic; + signal cs_b_en : std_logic; + signal rx_frame_start : std_logic; + + signal istat_lsbf : std_logic; + signal istat_hsbf : std_logic; + signal istat_paritya : std_logic; + signal istat_parityb : std_logic; + + signal sbuf_wr_adr : std_logic_vector(C_S_AXI_ADDR_WIDTH - 2 downto 0); + +begin + + ------------------------------------------------------------------------------- + -- Version Register'w + ------------------------------------------------------------------------------- + version_reg(31 downto 20) <= (others => '0'); + version_reg(19 downto 16) <= "0001"; + version_reg(15 downto 12) <= (others => '0'); + version_reg(11 downto 5) <= std_logic_vector(to_unsigned(C_S_AXI_ADDR_WIDTH,7)); + version_reg(4) <= '1'; + version_reg(3 downto 0) <= "0001"; + -------------------------------------------------------------------------------- + + -------------------------------------------------------------------------------- + -- Control Register + -------------------------------------------------------------------------------- + conf_mode(3 downto 0) <= control_reg(23 downto 20); + conf_paren <= control_reg(19); + conf_staten <= control_reg(18); + conf_useren <= control_reg(17); + conf_valen <= control_reg(16); + conf_blken <= control_reg(5); + conf_valid <= control_reg(4); + conf_chas <= control_reg(3); + evt_en <= control_reg(2); + conf_sample <= control_reg(1); + conf_rxen <= control_reg(0); + -------------------------------------------------------------------------------- + + fifo_reset <= not conf_sample; + enable <= conf_sample = '1'; + + streaming_dma_gen: if C_DMA_TYPE = 0 generate + fifo: entity axi_streaming_dma_rx_fifo + generic map ( + RAM_ADDR_WIDTH => 3, + FIFO_DWIDTH => 32 + ) + port map ( + clk => S_AXI_ACLK, + resetn => S_AXI_ARESETN, + fifo_reset => fifo_reset, + + enable => enable, + period_len => 11, + + M_AXIS_ACLK => M_AXIS_ACLK, + M_AXIS_TREADY => M_AXIS_TREADY, + M_AXIS_TDATA => M_AXIS_TDATA, + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TKEEP => M_AXIS_TKEEP, + + -- Write port + in_stb => sample_wr, + in_ack => sample_ack, + in_data => sample_din + ); + end generate; + + no_streaming_dma_gen: if C_DMA_TYPE /= 0 generate + M_AXIS_TVALID <= '0'; + M_AXIS_TLAST <= '0'; + M_AXIS_TKEEP <= "0000"; + end generate; + + pl330_dma_gen: if C_DMA_TYPE = 1 generate + tx_fifo_stb <= '1' when wr_addr = 3 and wr_stb = '1' else '0'; + + fifo: entity pl330_dma_fifo + generic map( + RAM_ADDR_WIDTH => 3, + FIFO_DWIDTH => 32, + FIFO_DIRECTION => 0 + ) + port map ( + clk => S_AXI_ACLK, + resetn => S_AXI_ARESETN, + fifo_reset => fifo_reset, + enable => enable, + + in_data => sample_din, + in_stb => tx_fifo_stb, + + out_ack => '1', + out_data => sampled_data, + + dclk => DMA_REQ_ACLK, + dresetn => DMA_REQ_RSTN, + davalid => DMA_REQ_DAVALID, + daready => DMA_REQ_DAREADY, + datype => DMA_REQ_DATYPE, + drvalid => DMA_REQ_DRVALID, + drready => DMA_REQ_DRREADY, + drtype => DMA_REQ_DRTYPE, + drlast => DMA_REQ_DRLAST + ); + end generate; + + no_pl330_dma_gen: if C_DMA_TYPE /= 1 generate + DMA_REQ_DAREADY <= '0'; + DMA_REQ_DRVALID <= '0'; + DMA_REQ_DRTYPE <= (others => '0'); + DMA_REQ_DRLAST <= '0'; + end generate; + + -------------------------------------------------------------------------------- + -- Status Register + -------------------------------------------------------------------------------- + STAT: rx_status_reg + generic map + ( + DATA_WIDTH => C_S_AXI_DATA_WIDTH + ) + port map + ( + up_clk => S_AXI_ACLK, + status_rd => rd_ack, + lock => lock, + chas => conf_chas, + rx_block_start => rx_block_start, + ch_data => rx_data, + cs_a_en => cs_a_en, + cs_b_en => cs_b_en, + status_dout => chstatus_reg + ); + -------------------------------------------------------------------------------- + + -------------------------------------------------------------------------------- + -- Phase decoder + -------------------------------------------------------------------------------- + PDET: rx_phase_det + generic map + ( + AXI_FREQ => 100 -- WishBone frequency in MHz + ) + port map + ( + up_clk => S_AXI_ACLK, + rxen => conf_rxen, + spdif => spdif_rx_i, + lock => lock, + lock_evt => lock_evt, + rx_data => rx_data, + rx_data_en => rx_data_en, + rx_block_start => rx_block_start, + rx_frame_start => rx_frame_start, + rx_channel_a => rx_channel_a, + rx_error => rx_error, + ud_a_en => ud_a_en, + ud_b_en => ud_b_en, + cs_a_en => cs_a_en, + cs_b_en => cs_b_en + ); + spdif_rx_i_osc <= spdif_rx_i; + -------------------------------------------------------------------------------- + + -------------------------------------------------------------------------------- + -- Rx Decoder + -------------------------------------------------------------------------------- + FDEC: rx_decode + generic map + ( + DATA_WIDTH => C_S_AXI_DATA_WIDTH, + ADDR_WIDTH => C_S_AXI_ADDR_WIDTH + ) + port map + ( + up_clk => S_AXI_ACLK, + conf_rxen => conf_rxen, + conf_sample => conf_sample, + conf_valid => conf_valid, + conf_mode => conf_mode, + conf_blken => conf_blken, + conf_valen => conf_valen, + conf_useren => conf_useren, + conf_staten => conf_staten, + conf_paren => conf_paren, + lock => lock, + rx_data => rx_data, + rx_data_en => rx_data_en, + rx_block_start => rx_block_start, + rx_frame_start => rx_frame_start, + rx_channel_a => rx_channel_a, + wr_en => sample_wr, + wr_addr => sbuf_wr_adr, + wr_data => sample_din, + stat_paritya => istat_paritya, + stat_parityb => istat_parityb, + stat_lsbf => istat_lsbf, + stat_hsbf => istat_hsbf + ); + rx_int_o <= sample_wr; + + ctrlif: entity axi_ctrlif + generic map ( + C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, + C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, + C_NUM_REG => 4 + ) + port map( + S_AXI_ACLK => S_AXI_ACLK, + S_AXI_ARESETN => S_AXI_ARESETN, + S_AXI_AWADDR => S_AXI_AWADDR, + S_AXI_AWVALID => S_AXI_AWVALID, + S_AXI_WDATA => S_AXI_WDATA, + S_AXI_WSTRB => S_AXI_WSTRB, + S_AXI_WVALID => S_AXI_WVALID, + S_AXI_BREADY => S_AXI_BREADY, + S_AXI_ARADDR => S_AXI_ARADDR, + S_AXI_ARVALID => S_AXI_ARVALID, + S_AXI_RREADY => S_AXI_RREADY, + S_AXI_ARREADY => S_AXI_ARREADY, + S_AXI_RDATA => S_AXI_RDATA, + S_AXI_RRESP => S_AXI_RRESP, + S_AXI_RVALID => S_AXI_RVALID, + S_AXI_WREADY => S_AXI_WREADY, + S_AXI_BRESP => S_AXI_BRESP, + S_AXI_BVALID => S_AXI_BVALID, + S_AXI_AWREADY => S_AXI_AWREADY, + + rd_addr => rd_addr, + rd_data => rd_data, + rd_ack => rd_ack, + rd_stb => '1', + + wr_addr => wr_addr, + wr_data => wr_data, + wr_ack => '1', + wr_stb => wr_stb + ); + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + version_reg <= (others => '0'); + control_reg <= (others => '0'); + else + if wr_stb = '1' then + case wr_addr is + when 0 => version_reg <= wr_data; + when 1 => control_reg <= wr_data; + when others => null; + end case; + end if; + end if; + end if; + end process; + + process (rd_addr, version_reg, control_reg, chstatus_reg) + begin + case rd_addr is + when 0 => rd_data <= version_reg; + when 1 => rd_data <= control_reg; + when 2 => rd_data <= chstatus_reg; + when 3 => rd_data <= sampled_data; + when others => rd_data <= (others => '0'); + end case; + end process; + +end IMP; diff --git a/library/axi_spdif_rx/axi_spdif_rx_constr.xdc b/library/axi_spdif_rx/axi_spdif_rx_constr.xdc new file mode 100644 index 000000000..e69de29bb diff --git a/library/axi_spdif_rx/axi_spdif_rx_ip.tcl b/library/axi_spdif_rx/axi_spdif_rx_ip.tcl new file mode 100644 index 000000000..edbe7f930 --- /dev/null +++ b/library/axi_spdif_rx/axi_spdif_rx_ip.tcl @@ -0,0 +1,52 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_spdif_rx +adi_ip_files axi_spdif_rx [list \ + "$ad_hdl_dir/library/common/axi_ctrlif.vhd" \ + "$ad_hdl_dir/library/common/axi_streaming_dma_rx_fifo.vhd" \ + "$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \ + "$ad_hdl_dir/library/common/dma_fifo.vhd" \ + "rx_phase_det.vhd" \ + "rx_package.vhd" \ + "rx_decode.vhd" \ + "rx_status_reg.vhd" \ + "axi_spdif_rx.vhd" \ + "axi_spdif_rx_constr.xdc"] + +adi_ip_properties_lite axi_spdif_rx +adi_ip_constraints axi_spdif_tx axi_spdif_rx_constr.xdc + +adi_add_bus "DMA_ACK" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"DMA_REQ_DAVALID" "TVALID"} \ + {"DMA_REQ_DAREADY" "TREADY"} \ + {"DMA_REQ_DATYPE" "TUSER"} ] +adi_add_bus "DMA_REQ" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"DMA_REQ_DRVALID" "TVALID"} \ + {"DMA_REQ_DRREADY" "TREADY"} \ + {"DMA_REQ_DRTYPE" "TUSER"} \ + {"DMA_REQ_DRLAST" "TLAST"} ] + +# Clock and reset are for both DMA_REQ and DMA_ACK +adi_add_bus_clock "DMA_REQ_ACLK" "DMA_REQ:DMA_ACK" "DMA_REQ_RSTN" + +adi_set_bus_dependency "M_AXIS" "M_AXIS" \ + "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)" + +adi_set_bus_dependency "DMA_ACK" "DMA_REQ_DA" \ + "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" +adi_set_bus_dependency "DMA_REQ" "DMA_REQ_DR" \ + "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" +adi_set_ports_dependency "DMA_REQ_ACLK" \ + "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" +adi_set_ports_dependency "DMA_REQ_RSTN" \ + "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" + +ipx::save_core [ipx::current_core] + diff --git a/library/axi_spdif_rx/rx_cap_reg.vhd b/library/axi_spdif_rx/rx_cap_reg.vhd new file mode 100644 index 000000000..ad7c24538 --- /dev/null +++ b/library/axi_spdif_rx/rx_cap_reg.vhd @@ -0,0 +1,176 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE SPDIF IP Core ---- +---- ---- +---- This file is part of the SPDIF project ---- +---- http://www.opencores.org/cores/spdif_interface/ ---- +---- ---- +---- Description ---- +---- SPDIF receiver channel status capture module ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.4 2004/07/19 16:58:37 gedra +-- Fixed bug. +-- +-- Revision 1.3 2004/06/27 16:16:55 gedra +-- Signal renaming and bug fix. +-- +-- Revision 1.2 2004/06/26 14:14:47 gedra +-- Converted to numeric_std and fixed a few bugs. +-- +-- Revision 1.1 2004/06/05 17:16:46 gedra +-- Channel status/user data capture register +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.rx_package.all; + +entity rx_cap_reg is + port ( + clk: in std_logic; -- clock + rst: in std_logic; -- reset + --cap_ctrl_wr: in std_logic; -- control register write + --cap_ctrl_rd: in std_logic; -- control register read + --cap_data_rd: in std_logic; -- data register read + cap_reg: in std_logic_vector(31 downto 0); + cap_din: in std_logic_vector(31 downto 0); -- write data + rx_block_start: in std_logic; -- start of block signal + ch_data: in std_logic; -- channel status/user data + ud_a_en: in std_logic; -- user data ch. A enable + ud_b_en: in std_logic; -- user data ch. B enable + cs_a_en: in std_logic; -- channel status ch. A enable + cs_b_en: in std_logic; -- channel status ch. B enable + cap_dout: out std_logic_vector(31 downto 0); -- read data + cap_evt: out std_logic); -- capture event (interrupt) +end rx_cap_reg; + +architecture rtl of rx_cap_reg is + + signal cap_ctrl_bits, cap_ctrl_dout: std_logic_vector(31 downto 0); + signal cap_reg_1, cap_new : std_logic_vector(31 downto 0); + signal bitlen, cap_len : integer range 0 to 63; + signal bitpos, cur_pos : integer range 0 to 255; + signal chid, cdata, compared : std_logic; + signal d_enable : std_logic_vector(3 downto 0); + +begin + +-- Data bus or'ing + cap_dout <= cap_reg_1;-- when cap_data_rd = '1' else cap_ctrl_dout; + + chid <= cap_reg(6); + cdata <= cap_reg(7); + +-- capture data register + CDAT: process (clk, rst) + begin + if rst = '1' then + cap_reg_1 <= (others => '0'); -- + cap_new <= (others => '0'); + cur_pos <= 0; + cap_len <= 0; + cap_evt <= '0'; + compared <= '0'; + bitpos <= 0; + bitlen <= 0; + else + if rising_edge(clk) then + bitlen <= to_integer(unsigned(cap_reg(5 downto 0))); + bitpos <= to_integer(unsigned(cap_reg(15 downto 8))); + if bitlen > 0 then -- bitlen = 0 disables the capture function + -- bit counter, 0 to 191 + if rx_block_start = '1' then + cur_pos <= 0; + cap_len <= 0; + cap_new <= (others => '0'); + compared <= '0'; + elsif cs_b_en = '1' then -- ch. status #2 comes last, count then + cur_pos <= cur_pos + 1; + end if; + -- capture bits + if cur_pos >= bitpos and cap_len < bitlen then + case d_enable is + when "0001" => -- user data channel A + if cdata = '0' and chid = '0' then + cap_new(cap_len) <= ch_data; + cap_len <= cap_len + 1; + end if; + when "0010" => -- user data channel B + if cdata = '0' and chid = '1' then + cap_new(cap_len) <= ch_data; + cap_len <= cap_len + 1; + end if; + when "0100" => -- channel status ch. A + if cdata = '1' and chid = '0' then + cap_new(cap_len) <= ch_data; + cap_len <= cap_len + 1; + end if; + when "1000" => -- channel status ch. B + if cdata = '1' and chid = '1' then + cap_new(cap_len) <= ch_data; + cap_len <= cap_len + 1; + end if; + when others => null; + end case; + end if; + -- if all bits captured, check with previous data + if cap_len = bitlen and compared = '0' then + compared <= '1'; + -- event generated if captured bits differ + if cap_reg_1 /= cap_new then + cap_evt <= '1'; + end if; + cap_reg_1 <= cap_new; + else + cap_evt <= '0'; + end if; + end if; + end if; + end if; + end process CDAT; + + d_enable(0) <= ud_a_en; + d_enable(1) <= ud_b_en; + d_enable(2) <= cs_a_en; + d_enable(3) <= cs_b_en; + +end rtl; diff --git a/library/axi_spdif_rx/rx_decode.vhd b/library/axi_spdif_rx/rx_decode.vhd new file mode 100644 index 000000000..a8f2585cf --- /dev/null +++ b/library/axi_spdif_rx/rx_decode.vhd @@ -0,0 +1,265 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE SPDIF IP Core ---- +---- ---- +---- This file is part of the SPDIF project ---- +---- http://www.opencores.org/cores/spdif_interface/ ---- +---- ---- +---- Description ---- +---- Sample decoder. Extract sample words and write to sample ---- +---- buffer. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.4 2004/07/11 16:19:50 gedra +-- Bug-fix. +-- +-- Revision 1.3 2004/06/26 14:14:47 gedra +-- Converted to numeric_std and fixed a few bugs. +-- +-- Revision 1.2 2004/06/16 19:04:09 gedra +-- Fixed a few bugs. +-- +-- Revision 1.1 2004/06/13 18:07:47 gedra +-- Frame decoder and sample extractor +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity rx_decode is + generic (DATA_WIDTH: integer range 16 to 32; + ADDR_WIDTH: integer range 8 to 64); + port ( + up_clk: in std_logic; + conf_rxen: in std_logic; + conf_sample: in std_logic; + conf_valid: in std_logic; + conf_mode: in std_logic_vector(3 downto 0); + conf_blken: in std_logic; + conf_valen: in std_logic; + conf_useren: in std_logic; + conf_staten: in std_logic; + conf_paren: in std_logic; + lock: in std_logic; + rx_data: in std_logic; + rx_data_en: in std_logic; + rx_block_start: in std_logic; + rx_frame_start: in std_logic; + rx_channel_a: in std_logic; + wr_en: out std_logic; + wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0); + wr_data: out std_logic_vector(DATA_WIDTH - 1 downto 0); + stat_paritya: out std_logic; + stat_parityb: out std_logic; + stat_lsbf: out std_logic; + stat_hsbf: out std_logic); +end rx_decode; + +architecture rtl of rx_decode is + + signal adr_cnt : integer range 0 to 2**(ADDR_WIDTH - 1) - 1; + type samp_states is (IDLE, CHA_SYNC, GET_SAMP, PAR_CHK); + signal sampst : samp_states; + signal bit_cnt, par_cnt : integer range 0 to 31; + signal samp_start : integer range 0 to 15; + signal tmp_data : std_logic_vector(31 downto 0); + signal tmp_stat : std_logic_vector(4 downto 0); + signal valid, next_is_a, blk_start : std_logic; + +begin + +-- output data + OD32: if DATA_WIDTH = 32 generate + --wr_data(31 downto 27) <= tmp_stat; + wr_data(31 downto 0) <= tmp_data(31 downto 0); + end generate OD32; + OD16: if DATA_WIDTH = 16 generate + wr_data(15 downto 0) <= tmp_data(15 downto 0); + end generate OD16; + +-- State machine extracting audio samples + SAEX: process (up_clk, conf_rxen) + begin -- process SAEX + if conf_rxen = '0' then + adr_cnt <= 0; + next_is_a <= '1'; + wr_en <= '0'; + wr_addr <= (others => '0'); + tmp_data <= (others => '0'); + par_cnt <= 0; + blk_start <= '0'; + stat_paritya <= '0'; + stat_parityb <= '0'; + stat_lsbf <= '0'; + stat_hsbf <= '0'; + valid <= '0'; + bit_cnt <= 0; + sampst <= IDLE; + tmp_stat <= (others => '0'); + elsif rising_edge(up_clk) then + --extract and store samples + case sampst is + when IDLE => + next_is_a <= '1'; + if lock = '1' and conf_sample = '1' then + sampst <= CHA_SYNC; + end if; + when CHA_SYNC => + wr_addr <= std_logic_vector(to_unsigned(adr_cnt, ADDR_WIDTH - 1)); + wr_en <= '0'; + bit_cnt <= 0; + valid <= '0'; + par_cnt <= 0; + stat_paritya <= '0'; + stat_parityb <= '0'; + stat_lsbf <= '0'; + stat_hsbf <= '0'; + --tmp_data(31 downto 0) <= (others => '0'); + if rx_block_start = '1' and conf_blken = '1' then + blk_start <= '1'; + end if; + if rx_frame_start = '1' then --and rx_channel_a = '1' then --next_is_a then + next_is_a <= rx_channel_a; + if(rx_channel_a = '1') then + tmp_data(31 downto 0) <= (others => '0'); + end if; + sampst <= GET_SAMP; + end if; + when GET_SAMP => + tmp_stat(0) <= blk_start; + if rx_data_en = '1' then + bit_cnt <= bit_cnt + 1; + -- audio part + if bit_cnt >= samp_start and bit_cnt <= 23 then + if(next_is_a = '1') then + tmp_data(bit_cnt - samp_start) <= rx_data; + else + tmp_data(bit_cnt + 16 - samp_start) <= rx_data; + end if; + end if; + -- status bits + case bit_cnt is + when 24 => -- validity bit + valid <= rx_data; + if conf_valen = '1' then + tmp_stat(1) <= rx_data; + else + tmp_stat(1) <= '0'; + end if; + when 25 => -- user data + if conf_useren = '1' then + tmp_stat(2) <= rx_data; + else + tmp_stat(2) <= '0'; + end if; + when 26 => -- channel status + if conf_staten = '1' then + tmp_stat(3) <= rx_data; + else + tmp_stat(3) <= '0'; + end if; + when 27 => -- parity bit + if conf_paren = '1' then + tmp_stat(4) <= rx_data; + else + tmp_stat(4) <= '0'; + end if; + when others => + null; + end case; + -- parity: count number of 1's + if rx_data = '1' then + par_cnt <= par_cnt + 1; + end if; + end if; + if bit_cnt = 28 then + sampst <= PAR_CHK; + end if; + when PAR_CHK => + blk_start <= '0'; + if (((valid = '0' and conf_valid = '1') or conf_valid = '0') and (next_is_a = '0')) then + wr_en <= '1'; + end if; + -- parity check + if par_cnt mod 2 /= 0 then + if rx_channel_a = '1' then + stat_paritya <= '1'; + else + stat_parityb <= '1'; + end if; + end if; + -- address counter + if adr_cnt < 2**(ADDR_WIDTH - 1) - 1 then + adr_cnt <= adr_cnt + 1; + else + adr_cnt <= 0; + stat_hsbf <= '1'; -- signal high buffer full + end if; + if adr_cnt = 2**(ADDR_WIDTH - 2) - 1 then + stat_lsbf <= '1'; -- signal low buffer full + end if; + sampst <= CHA_SYNC; + when others => + sampst <= IDLE; + end case; + end if; + end process SAEX; + +-- determine sample resolution from mode bits in 32bit mode + M32: if DATA_WIDTH = 32 generate + samp_start <= 8 when conf_mode = "0000" else + 7 when conf_mode = "0001" else + 6 when conf_mode = "0010" else + 5 when conf_mode = "0011" else + 4 when conf_mode = "0100" else + 3 when conf_mode = "0101" else + 2 when conf_mode = "0110" else + 1 when conf_mode = "0111" else + 0 when conf_mode = "1000" else + 8; + end generate M32; +-- in 16bit mode only 16bit of audio is supported + M16: if DATA_WIDTH = 16 generate + samp_start <= 8; + end generate M16; + + +end rtl; diff --git a/library/axi_spdif_rx/rx_package.vhd b/library/axi_spdif_rx/rx_package.vhd new file mode 100644 index 000000000..8df4c9fd0 --- /dev/null +++ b/library/axi_spdif_rx/rx_package.vhd @@ -0,0 +1,248 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE SPDIF IP Core ---- +---- ---- +---- This file is part of the SPDIF project ---- +---- http://www.opencores.org/cores/spdif_interface/ ---- +---- ---- +---- Description ---- +---- SPDIF receiver component package. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.8 2004/06/27 16:16:55 gedra +-- Signal renaming and bug fix. +-- +-- Revision 1.7 2004/06/26 14:14:47 gedra +-- Converted to numeric_std and fixed a few bugs. +-- +-- Revision 1.6 2004/06/23 18:10:17 gedra +-- Added Wishbone bus cycle decoder. +-- +-- Revision 1.5 2004/06/16 19:03:45 gedra +-- Changed status reg. declaration +-- +-- Revision 1.4 2004/06/13 18:08:09 gedra +-- Added frame decoder and sample extractor +-- +-- Revision 1.3 2004/06/10 18:57:36 gedra +-- Cleaned up lint warnings. +-- +-- Revision 1.2 2004/06/09 19:24:50 gedra +-- Added dual port ram. +-- +-- Revision 1.1 2004/06/07 18:06:00 gedra +-- Receiver component declarations. +-- +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package rx_package is + +-- type declarations + type bus_array is array (0 to 7) of std_logic_vector(31 downto 0); + +-- components + component rx_ver_reg + generic (DATA_WIDTH: integer := 32; + ADDR_WIDTH: integer := 8; + CH_ST_CAPTURE: integer := 1); + port ( + ver_rd: in std_logic; -- version register read + ver_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0)); -- read data + end component; + + component gen_control_reg + generic (DATA_WIDTH: integer; + -- note that this vector is (0 to xx), reverse order + ACTIVE_BIT_MASK: std_logic_vector); + port ( + clk: in std_logic; -- clock + rst: in std_logic; -- reset + ctrl_wr: in std_logic; -- control register write + ctrl_rd: in std_logic; -- control register read + ctrl_din: in std_logic_vector(DATA_WIDTH - 1 downto 0); + ctrl_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0); + ctrl_bits: out std_logic_vector(DATA_WIDTH - 1 downto 0)); + end component; + + component rx_status_reg + generic (DATA_WIDTH: integer := 32); + port ( + up_clk: in std_logic; -- clock + status_rd: in std_logic; -- status register read + lock: in std_logic; -- signal lock status + chas: in std_logic; -- channel A or B select + rx_block_start: in std_logic; -- start of block signal + ch_data: in std_logic; -- channel status/user data + cs_a_en: in std_logic; -- channel status ch. A enable + cs_b_en: in std_logic; -- channel status ch. B enable + status_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0)); + end component; + + component gen_event_reg + generic (DATA_WIDTH: integer := 32); + port ( + clk: in std_logic; -- clock + rst: in std_logic; -- reset + evt_wr: in std_logic; -- event register write + evt_rd: in std_logic; -- event register read + evt_din: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data + event: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- event vector + evt_mask: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- irq mask + evt_en: in std_logic; -- irq enable + evt_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data + evt_irq: out std_logic); -- interrupt request + end component; + + component rx_cap_reg + port ( + clk: in std_logic; -- clock + rst: in std_logic; -- reset + --cap_ctrl_wr: in std_logic; -- control register write + --cap_ctrl_rd: in std_logic; -- control register read + --cap_data_rd: in std_logic; -- data register read + cap_reg: in std_logic_vector(31 downto 0); + cap_din: in std_logic_vector(31 downto 0); -- write data + rx_block_start: in std_logic; -- start of block signal + ch_data: in std_logic; -- channel status/user data + ud_a_en: in std_logic; -- user data ch. A enable + ud_b_en: in std_logic; -- user data ch. B enable + cs_a_en: in std_logic; -- channel status ch. A enable + cs_b_en: in std_logic; -- channel status ch. B enable + cap_dout: out std_logic_vector(31 downto 0); -- read data + cap_evt: out std_logic); -- capture event (interrupt) + end component; + + component rx_phase_det + generic (AXI_FREQ: natural := 33); -- WishBone frequency in MHz + port ( + up_clk: in std_logic; + rxen: in std_logic; + spdif: in std_logic; + lock: out std_logic; + lock_evt: out std_logic; -- lock status change event + rx_data: out std_logic; + rx_data_en: out std_logic; + rx_block_start: out std_logic; + rx_frame_start: out std_logic; + rx_channel_a: out std_logic; + rx_error: out std_logic; + ud_a_en: out std_logic; -- user data ch. A enable + ud_b_en: out std_logic; -- user data ch. B enable + cs_a_en: out std_logic; -- channel status ch. A enable + cs_b_en: out std_logic); -- channel status ch. B enable); + end component; + + component dpram + generic (DATA_WIDTH: positive := 32; + RAM_WIDTH: positive := 8); + port ( + clk: in std_logic; + rst: in std_logic; -- reset is optional, not used here + din: in std_logic_vector(DATA_WIDTH - 1 downto 0); + wr_en: in std_logic; + rd_en: in std_logic; + wr_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0); + rd_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0); + dout: out std_logic_vector(DATA_WIDTH - 1 downto 0)); + end component; + + component rx_decode + generic (DATA_WIDTH: integer range 16 to 32 := 32; + ADDR_WIDTH: integer range 8 to 64 := 8); + port ( + up_clk: in std_logic; + conf_rxen: in std_logic; + conf_sample: in std_logic; + conf_valid: in std_logic; + conf_mode: in std_logic_vector(3 downto 0); + conf_blken: in std_logic; + conf_valen: in std_logic; + conf_useren: in std_logic; + conf_staten: in std_logic; + conf_paren: in std_logic; + lock: in std_logic; + rx_data: in std_logic; + rx_data_en: in std_logic; + rx_block_start: in std_logic; + rx_frame_start: in std_logic; + rx_channel_a: in std_logic; + wr_en: out std_logic; + wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0); + wr_data: out std_logic_vector(DATA_WIDTH - 1 downto 0); + stat_paritya: out std_logic; + stat_parityb: out std_logic; + stat_lsbf: out std_logic; + stat_hsbf: out std_logic); + end component; + + component rx_wb_decoder + generic (DATA_WIDTH: integer := 32; + ADDR_WIDTH: integer := 8); + port ( + up_clk: in std_logic; -- wishbone clock + wb_rst_i: in std_logic; -- reset signal + wb_sel_i: in std_logic; -- select input + wb_stb_i: in std_logic; -- strobe input + wb_we_i: in std_logic; -- write enable + wb_cyc_i: in std_logic; -- cycle input + wb_bte_i: in std_logic_vector(1 downto 0); -- burts type extension + wb_adr_i: in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address + wb_cti_i: in std_logic_vector(2 downto 0); -- cycle type identifier + data_out: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus + wb_ack_o: out std_logic; -- acknowledge + wb_dat_o: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out + version_rd: out std_logic; -- Version register read + config_rd: out std_logic; -- Config register read + config_wr: out std_logic; -- Config register write + status_rd: out std_logic; -- Status register read + intmask_rd: out std_logic; -- Interrupt mask register read + intmask_wr: out std_logic; -- Interrupt mask register write + intstat_rd: out std_logic; -- Interrupt status register read + intstat_wr: out std_logic; -- Interrupt status register read + mem_rd: out std_logic; -- Sample memory read + mem_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- memory addr. + ch_st_cap_rd: out std_logic_vector(7 downto 0); -- Ch. status cap. read + ch_st_cap_wr: out std_logic_vector(7 downto 0); -- Ch. status cap. write + ch_st_data_rd: out std_logic_vector(7 downto 0)); -- Ch. status data read + end component; + +end rx_package; diff --git a/library/axi_spdif_rx/rx_phase_det.vhd b/library/axi_spdif_rx/rx_phase_det.vhd new file mode 100644 index 000000000..f99b14736 --- /dev/null +++ b/library/axi_spdif_rx/rx_phase_det.vhd @@ -0,0 +1,398 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE SPDIF IP Core ---- +---- ---- +---- This file is part of the SPDIF project ---- +---- http://www.opencores.org/cores/spdif_interface/ ---- +---- ---- +---- Description ---- +---- Oversampling phase detector. Decodes bi-phase mark encoded ---- +---- signal. Clock must be at least 8 times higher than bit rate. ---- +---- The SPDIF bitrate must be minimum 100kHz. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.5 2004/07/19 16:58:37 gedra +-- Fixed bug. +-- +-- Revision 1.4 2004/07/12 17:06:41 gedra +-- Fixed bug with lock event generation. +-- +-- Revision 1.3 2004/07/11 16:19:50 gedra +-- Bug-fix. +-- +-- Revision 1.2 2004/06/13 18:08:50 gedra +-- Renamed generic and cleaned some lint's +-- +-- Revision 1.1 2004/06/06 15:43:02 gedra +-- Early version of the bi-phase mark decoder. +-- +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity rx_phase_det is + generic (AXI_FREQ: natural := 100); -- WishBone frequency in MHz + port ( + up_clk: in std_logic; -- wishbone clock + rxen: in std_logic; -- phase detector enable + spdif: in std_logic; -- SPDIF input signal + lock: out std_logic; -- true if locked to spdif input + lock_evt: out std_logic; -- lock status change event + rx_data: out std_logic; -- recevied data + rx_data_en: out std_logic; -- received data enable + rx_block_start: out std_logic; -- start-of-block pulse + rx_frame_start: out std_logic; -- start-of-frame pulse + rx_channel_a: out std_logic; -- 1 if channel A frame is recevied + rx_error: out std_logic; -- signal error was detected + ud_a_en: out std_logic; -- user data ch. A enable + ud_b_en: out std_logic; -- user data ch. B enable + cs_a_en: out std_logic; -- channel status ch. A enable + cs_b_en: out std_logic); -- channel status ch. B enable); +end rx_phase_det; + +architecture rtl of rx_phase_det is + + constant TRANSITIONS : integer := 70; + constant FRAMES_FOR_LOCK : integer := 3; + signal maxpulse, maxp, mp_cnt: integer range 0 to 16 * AXI_FREQ; + signal last_cnt, max_thres : integer range 0 to 16 * AXI_FREQ; + signal minpulse, minp, min_thres: integer range 0 to 8 * AXI_FREQ; + signal zspdif, spdif_in, zspdif_in, trans, ztrans : std_logic; + signal trans_cnt : integer range 0 to TRANSITIONS; + signal valid, p_long, p_short: std_logic; + type pulse_type is (ZERO, SHORT, MED, LONG); + type pulse_array is array (0 to 3) of pulse_type; + signal preamble: pulse_array; + signal new_pulse, short_idx, ilock: std_logic; + type frame_state is (IDLE, HUNT, FRAMESTART, FRAME_RX); + signal framerx : frame_state; + signal frame_cnt : integer range 0 to FRAMES_FOR_LOCK; + signal bit_cnt : integer range 0 to 63; + signal pre_cnt : integer range 0 to 7; + type preamble_types is (NONE, PRE_X, PRE_Y, PRE_Z); + signal new_preamble, last_preamble : preamble_types; + signal irx_channel_a, zilock : std_logic; + +begin + + -- Pulse width analyzer + PHDET: process (up_clk, rxen) + begin + if rxen = '0' then -- reset by configuration register bit + maxpulse <= 0; + maxp <= 0; + mp_cnt <= 0; + zspdif <= '0'; + zspdif_in <= '0'; + spdif_in <= '0'; + trans_cnt <= 0; + minpulse <= 0; + minp <= 8 * AXI_FREQ; + last_cnt <= 0; + trans <= '0'; + valid <= '0'; + preamble <= (ZERO, ZERO, ZERO, ZERO); + max_thres <= 0; + min_thres <= 0; + new_preamble <= NONE; + ztrans <= '0'; + new_pulse <= '0'; + else + if rising_edge(up_clk) then + -- sync spdif signal to wishbone clock + zspdif <= spdif; + spdif_in <= zspdif; + -- find the longest pulse, which is the bi-phase violation + -- also find the shortest pulse + zspdif_in <= spdif_in; + if zspdif_in /= spdif_in then -- input transition + mp_cnt <= 0; + trans <= '1'; + last_cnt <= mp_cnt; + if trans_cnt > 0 then + if mp_cnt > maxp then + maxp <= mp_cnt; + end if; + if mp_cnt < minp then + minp <= mp_cnt; + end if; + end if; + else + trans <= '0'; + if mp_cnt < 16 * AXI_FREQ then + mp_cnt <= mp_cnt + 1; + end if; + end if; + -- transition counting + if trans = '1' then + if trans_cnt < TRANSITIONS then + trans_cnt <= trans_cnt + 1; + else + -- the max/min pulse length is updated after given # of transitions + trans_cnt <= 0; + maxpulse <= maxp; + maxp <= 0; + minpulse <= minp; + minp <= 8 * AXI_FREQ; + min_thres <= maxp / 2; + if maxp < 11 then + max_thres <= maxp - 1; + else + max_thres <= maxp - 3; + end if; + end if; + end if; + -- detection of valid SPDIF signal + if maxpulse > 6 then + valid <= '1'; + else + valid <= '0'; + end if; + -- bit decoding + if trans = '1' then + if (last_cnt < min_thres) and (last_cnt > 0) then + p_short <= '1'; + preamble(0) <= SHORT; + else + p_short <= '0'; + end if; + if last_cnt >= max_thres then + p_long <= '1'; + preamble(0) <= LONG; + else + p_long <= '0'; + end if; + if last_cnt = 0 then + preamble(0) <= ZERO; + end if; + if (last_cnt < max_thres) and (last_cnt >= min_thres) then + preamble(0) <= MED; + end if; + preamble(3) <= preamble(2); + preamble(2) <= preamble(1); + preamble(1) <= preamble(0); + end if; + -- preamble detection + if preamble(3) = LONG and preamble(2) = LONG and preamble(1) = SHORT + and preamble(0) = SHORT then + new_preamble <= PRE_X; + elsif preamble(3) = LONG and preamble(2) = MED and preamble(1) = SHORT + and preamble(0) = MED then + new_preamble <= PRE_Y; + elsif preamble(3) = LONG and preamble(2) = SHORT and preamble(1) = SHORT + and preamble(0) = LONG then + new_preamble <= PRE_Z; + else + new_preamble <= NONE; + end if; + -- delayed transition pulse for the state machine + ztrans <= trans; + new_pulse <= ztrans; + end if; + end if; + end process; + + lock <= ilock; + rx_channel_a <= irx_channel_a; + + -- State machine that hunt for and lock onto sub-frames + FRX: process (up_clk, rxen) + begin + if rxen = '0' then + framerx <= IDLE; + ilock <= '0'; + zilock <= '0'; + rx_data <= '0'; + rx_data_en <= '0'; + rx_block_start <= '0'; + rx_frame_start <= '0'; + irx_channel_a <= '0'; + ud_a_en <= '0'; + ud_b_en <= '0'; + cs_a_en <= '0'; + cs_b_en <= '0'; + rx_error <= '0'; + lock_evt <= '0'; + bit_cnt <= 0; + pre_cnt <= 0; + short_idx <= '0'; + frame_cnt <= 0; + last_preamble <= NONE; + elsif rising_edge(up_clk) then + zilock <= ilock; + if zilock /= ilock then -- generate event for event reg. + lock_evt <= '1'; + else + lock_evt <= '0'; + end if; + case framerx is + when IDLE => -- wait for recevier to be enabled + if valid = '1' then + framerx <= HUNT; + end if; + when HUNT => -- wait for preamble detection + frame_cnt <= 0; + ilock <= '0'; + rx_error <= '0'; + if new_pulse = '1' then + if new_preamble /= NONE then + framerx <= FRAMESTART; + end if; + end if; + when FRAMESTART => -- reset sub-frame bit counter + bit_cnt <= 0; + pre_cnt <= 0; + if frame_cnt < FRAMES_FOR_LOCK then + frame_cnt <= frame_cnt + 1; + else + ilock <= '1'; + end if; + last_preamble <= new_preamble; + short_idx <= '0'; + rx_frame_start <= '1'; + rx_block_start <= '0'; + framerx <= FRAME_RX; + when FRAME_RX => -- receive complete sub-frame + if new_pulse = '1' then + if bit_cnt < 28 then + case preamble(0) is + when ZERO => + short_idx <= '0'; + when SHORT => + if short_idx = '0' then + short_idx <= '1'; + else + -- two short pulses is a logical '1' + bit_cnt <= bit_cnt + 1; + short_idx <= '0'; + rx_data <= '1'; + rx_data_en <= ilock; + -- user data enable for the capture register + if bit_cnt = 25 and ilock = '1' then + ud_a_en <= irx_channel_a; + ud_b_en <= not irx_channel_a; + end if; + -- channel status enable for the capture register + if bit_cnt = 26 and ilock = '1' then + cs_a_en <= irx_channel_a; + cs_b_en <= not irx_channel_a; + end if; + end if; + when MED => + -- medium pulse is logical '0' + bit_cnt <= bit_cnt + 1; + rx_data <= '0'; + rx_data_en <= ilock; + short_idx <= '0'; + -- user data enable for the capture register + if bit_cnt = 25 and ilock = '1' then + ud_a_en <= irx_channel_a; + ud_b_en <= not irx_channel_a; + end if; + -- channel status enable for the capture register + if bit_cnt = 26 and ilock = '1' then + cs_a_en <= irx_channel_a; + cs_b_en <= not irx_channel_a; + end if; + when LONG => + short_idx <= '0'; + when others => + framerx <= HUNT; + end case; + else + -- there should be 4 pulses in preamble + if pre_cnt < 7 then + pre_cnt <= pre_cnt + 1; + else + rx_error <= '1'; + framerx <= HUNT; + end if; + -- check for correct preamble here + if pre_cnt = 3 then + case last_preamble is + when PRE_X => + if new_preamble = PRE_Y then + framerx <= FRAMESTART; + irx_channel_a <= '0'; + else + rx_error <= '1'; + framerx <= HUNT; + end if; + when PRE_Y => + if new_preamble = PRE_X or new_preamble = PRE_Z then + irx_channel_a <= '1'; + -- start of new block? + if new_preamble = PRE_Z then + rx_block_start <= '1'; + end if; + framerx <= FRAMESTART; + else + rx_error <= '1'; + framerx <= HUNT; + end if; + when PRE_Z => + if new_preamble = PRE_Y then + irx_channel_a <= '0'; + framerx <= FRAMESTART; + else + rx_error <= '1'; + framerx <= HUNT; + end if; + when others => + rx_error <= '1'; + framerx <= HUNT; + end case; + end if; + end if; + else + rx_data_en <= '0'; + rx_block_start <= '0'; + rx_frame_start <= '0'; + ud_a_en <= '0'; + ud_b_en <= '0'; + cs_a_en <= '0'; + cs_b_en <= '0'; + end if; + when others => + framerx <= IDLE; + end case; + end if; + end process FRX; + +end rtl; diff --git a/library/axi_spdif_rx/rx_status_reg.vhd b/library/axi_spdif_rx/rx_status_reg.vhd new file mode 100644 index 000000000..afd9576b0 --- /dev/null +++ b/library/axi_spdif_rx/rx_status_reg.vhd @@ -0,0 +1,150 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE SPDIF IP Core ---- +---- ---- +---- This file is part of the SPDIF project ---- +---- http://www.opencores.org/cores/spdif_interface/ ---- +---- ---- +---- Description ---- +---- SPDIF receiver status register ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.4 2004/06/27 16:16:55 gedra +-- Signal renaming and bug fix. +-- +-- Revision 1.3 2004/06/26 14:14:47 gedra +-- Converted to numeric_std and fixed a few bugs. +-- +-- Revision 1.2 2004/06/16 19:03:10 gedra +-- Added channel status decoding. +-- +-- Revision 1.1 2004/06/05 17:17:12 gedra +-- Recevier status register +-- +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity rx_status_reg is + generic (DATA_WIDTH: integer); + port ( + up_clk: in std_logic; -- clock + status_rd: in std_logic; -- status register read + lock: in std_logic; -- signal lock status + chas: in std_logic; -- channel A or B select + rx_block_start: in std_logic; -- start of block signal + ch_data: in std_logic; -- channel status/user data + cs_a_en: in std_logic; -- channel status ch. A enable + cs_b_en: in std_logic; -- channel status ch. B enable + status_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0)); +end rx_status_reg; + +architecture rtl of rx_status_reg is + + signal status_vector : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal cur_pos : integer range 0 to 255; + signal pro_mode : std_logic; + +begin + + status_dout <= status_vector when status_rd = '1' else (others => '0'); + + D32: if DATA_WIDTH = 32 generate + status_vector(31 downto 16) <= (others => '0'); + end generate D32; + + status_vector(0) <= lock; + status_vector(15 downto 7) <= (others => '0'); + +-- extract channel status bits to be used + CDAT: process (up_clk, lock) + begin + if lock = '0' then + cur_pos <= 0; + pro_mode <= '0'; + status_vector(6 downto 1) <= (others => '0'); + else + if rising_edge(up_clk) then + -- bit counter, 0 to 191 + if rx_block_start = '1' then + cur_pos <= 0; + elsif cs_b_en = '1' then -- ch. status #2 comes last, count then + cur_pos <= cur_pos + 1; + end if; + -- extract status bits used in status register + if (chas = '0' and cs_b_en = '1') or + (chas = '1' and cs_a_en = '1') then + case cur_pos is + when 0 => -- PRO bit + status_vector(1) <= ch_data; + pro_mode <= ch_data; + when 1 => -- AUDIO bit + status_vector(2) <= not ch_data; + when 2 => -- emphasis/copy bit + if pro_mode = '1' then + status_vector(5) <= ch_data; + else + status_vector(6) <= ch_data; + end if; + when 3 => -- emphasis + if pro_mode = '1' then + status_vector(4) <= ch_data; + else + status_vector(5) <= ch_data; + end if; + when 4 => -- emphasis + if pro_mode = '1' then + status_vector(3) <= ch_data; + else + status_vector(4) <= ch_data; + end if; + when 5 => -- emphasis + if pro_mode = '0' then + status_vector(3) <= ch_data; + end if; + when others => + null; + end case; + end if; + end if; + end if; + end process CDAT; + +end rtl;