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ad9081: Versal transceiver update 

- Remove 4 lane limitation
- Adds support for RX or TX only instantiation

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
main
Bogdan Luncan 2023-02-02 09:18:59 +00:00 committed by Bogdan Luncan
parent e6ac64c532
commit 73af87a324
8 changed files with 604 additions and 445 deletions
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projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
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@ -10,7 +10,11 @@
# [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_NP : Number of bits per sample
# [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices
#
# INTF_CFG : Used to select betwen RX, TX or RX & TX
# RXTX : RX & TX
# RX : RX only
# Tx : TX only
if {![info exists ADI_PHY_SEL]} {
set ADI_PHY_SEL 1
}
@ -19,6 +23,8 @@ source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
source $ad_hdl_dir/library/axi_tdd/scripts/axi_tdd.tcl
set INTF_CFG $ad_project_params(INTF_CFG)
# Common parameter for TX and RX
set JESD_MODE $ad_project_params(JESD_MODE)
set RX_LANE_RATE $ad_project_params(RX_LANE_RATE)
@ -38,6 +44,10 @@ if {$TDD_SUPPORT && !$SHARED_DEVCLK} {
error "ERROR: Cannot enable TDD support without shared deviceclocks!"
}
if {$TDD_SUPPORT && $INTF_CFG != "RXTX"} {
error "ERROR: Cannot enable TDD support with INTF_CFG != RXTX!"
}
set adc_do_mem_type [ expr { [info exists ad_project_params(ADC_DO_MEM_TYPE)] \
? $ad_project_params(ADC_DO_MEM_TYPE) : 0 } ]
set dac_do_mem_type [ expr { [info exists ad_project_params(DAC_DO_MEM_TYPE)] \
@ -110,6 +120,8 @@ set TX_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $TX_JESD_L $TX
set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 8* $TX_DATAPATH_WIDTH / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)]
set num_quads [expr int(round(1.0 * $RX_NUM_OF_LANES / 4))]
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
set adc_data_offload_name mxfe_rx_data_offload
@ -122,154 +134,190 @@ set dac_data_width [expr $TX_DMA_SAMPLE_WIDTH*$TX_NUM_OF_CONVERTERS*$TX_SAMPLES_
set dac_dma_data_width $dac_data_width
set dac_fifo_address_width [expr int(ceil(log(($dac_fifo_samples_per_converter*$TX_NUM_OF_CONVERTERS) / ($dac_data_width/$TX_DMA_SAMPLE_WIDTH))/log(2)))]
create_bd_port -dir I rx_device_clk
create_bd_port -dir I tx_device_clk
# common xcvr
if {$ADI_PHY_SEL == 1} {
ad_ip_instance util_adxcvr util_mxfe_xcvr
ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_FBDIV_4_5 5
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_OUT_DIV 1
ad_ip_parameter util_mxfe_xcvr CONFIG.LINK_MODE $ENCODER_SEL
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_LANE_RATE $RX_LANE_RATE
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_LANE_RATE $TX_LANE_RATE
switch $INTF_CFG {
"RXTX" {
# Rx & Tx
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_OUT_DIV 1
ad_ip_parameter util_mxfe_xcvr CONFIG.LINK_MODE $ENCODER_SEL
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_LANE_RATE $RX_LANE_RATE
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_LANE_RATE $TX_LANE_RATE
}
"RX" {
# Rx only
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_NUM_OF_LANES 0
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_OUT_DIV 1
ad_ip_parameter util_mxfe_xcvr CONFIG.LINK_MODE $ENCODER_SEL
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_LANE_RATE $RX_LANE_RATE
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_LANE_RATE 0
}
"TX" {
# Tx only
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_NUM_OF_LANES 0
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_OUT_DIV 1
ad_ip_parameter util_mxfe_xcvr CONFIG.LINK_MODE $ENCODER_SEL
ad_ip_parameter util_mxfe_xcvr CONFIG.RX_LANE_RATE 0
ad_ip_parameter util_mxfe_xcvr CONFIG.TX_LANE_RATE $TX_LANE_RATE
}
}
} else {
source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl
set REF_CLK_RATE [ expr { [info exists ad_project_params(REF_CLK_RATE)] \
? $ad_project_params(REF_CLK_RATE) : 360 } ]
# TODO:
# Assumption is that number of Tx and Rx lane is the same
create_versal_phy jesd204_phy $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE
switch $INTF_CFG {
"RXTX" {
# Assumption is that number of Tx and Rx lane is the same
create_versal_phy jesd204_phy $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $INTF_CFG
}
"RX" {
create_versal_phy jesd204_phy $RX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $INTF_CFG
}
"TX" {
create_versal_phy jesd204_phy $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $INTF_CFG
}
}
}
if {$ADI_PHY_SEL == 1} {
ad_ip_instance axi_adxcvr axi_mxfe_rx_xcvr
ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.ID 0
ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.LINK_MODE $ENCODER_SEL
ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.LPM_OR_DFE_N 1
ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.SYS_CLK_SEL 0x3 ; # QPLL0
# Instantiate ADC (Rx) path
if {$INTF_CFG != "TX"} {
create_bd_port -dir I rx_device_clk
ad_ip_instance axi_adxcvr axi_mxfe_tx_xcvr
ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.ID 0
ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.LINK_MODE $ENCODER_SEL
ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.TX_OR_RX_N 1
ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.SYS_CLK_SEL 0x3 ; # QPLL0
if {$ADI_PHY_SEL == 1} {
ad_ip_instance axi_adxcvr axi_mxfe_rx_xcvr
ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.ID 0
ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.LINK_MODE $ENCODER_SEL
ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.LPM_OR_DFE_N 1
ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.SYS_CLK_SEL 0x3 ; # QPLL0
}
if {$ADI_PHY_SEL == 0} {
# reset generator
ad_ip_instance proc_sys_reset rx_device_clk_rstgen
ad_connect rx_device_clk rx_device_clk_rstgen/slowest_sync_clk
ad_connect $sys_cpu_resetn rx_device_clk_rstgen/ext_reset_in
}
adi_axi_jesd204_rx_create axi_mxfe_rx_jesd $RX_NUM_OF_LANES $RX_NUM_LINKS $ENCODER_SEL
ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.TPL_DATA_PATH_WIDTH $RX_DATAPATH_WIDTH
ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.SYSREF_IOB false
ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 1
adi_tpl_jesd204_rx_create rx_mxfe_tpl_core $RX_NUM_OF_LANES \
$RX_NUM_OF_CONVERTERS \
$RX_SAMPLES_PER_FRAME \
$RX_SAMPLE_WIDTH \
$RX_DATAPATH_WIDTH \
$RX_DMA_SAMPLE_WIDTH
ad_ip_instance util_cpack2 util_mxfe_cpack [list \
NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $RX_DMA_SAMPLE_WIDTH \
]
set adc_data_offload_size [expr $adc_data_width / 8 * 2**$adc_fifo_address_width]
ad_data_offload_create $adc_data_offload_name \
0 \
$adc_do_mem_type \
$adc_data_offload_size \
$adc_data_width \
$adc_data_width \
$do_axi_data_width \
$SHARED_DEVCLK
ad_ip_instance axi_dmac axi_mxfe_rx_dma
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_mxfe_rx_dma CONFIG.ID 0
ad_ip_parameter axi_mxfe_rx_dma CONFIG.AXI_SLICE_SRC 1
ad_ip_parameter axi_mxfe_rx_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_mxfe_rx_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_mxfe_rx_dma CONFIG.MAX_BYTES_PER_BURST 4096
ad_ip_parameter axi_mxfe_rx_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $dac_dma_data_width
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_DEST [expr min(512, $dac_dma_data_width)]
}
if {$ADI_PHY_SEL == 0} {
# reset generator
ad_ip_instance proc_sys_reset rx_device_clk_rstgen
ad_connect rx_device_clk rx_device_clk_rstgen/slowest_sync_clk
ad_connect $sys_cpu_resetn rx_device_clk_rstgen/ext_reset_in
# Instantiate DAC (Tx) path
if {$INTF_CFG != "RX"} {
create_bd_port -dir I tx_device_clk
ad_ip_instance proc_sys_reset tx_device_clk_rstgen
ad_connect tx_device_clk tx_device_clk_rstgen/slowest_sync_clk
ad_connect $sys_cpu_resetn tx_device_clk_rstgen/ext_reset_in
if {$ADI_PHY_SEL == 1} {
ad_ip_instance axi_adxcvr axi_mxfe_tx_xcvr
ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.ID 0
ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.LINK_MODE $ENCODER_SEL
ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.TX_OR_RX_N 1
ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.SYS_CLK_SEL 0x3 ; # QPLL0
}
if {$ADI_PHY_SEL == 0} {
# reset generator
ad_ip_instance proc_sys_reset tx_device_clk_rstgen
ad_connect tx_device_clk tx_device_clk_rstgen/slowest_sync_clk
ad_connect $sys_cpu_resetn tx_device_clk_rstgen/ext_reset_in
}
adi_axi_jesd204_tx_create axi_mxfe_tx_jesd $TX_NUM_OF_LANES $TX_NUM_LINKS $ENCODER_SEL
ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.TPL_DATA_PATH_WIDTH $TX_DATAPATH_WIDTH
ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.SYSREF_IOB false
#ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1
adi_tpl_jesd204_tx_create tx_mxfe_tpl_core $TX_NUM_OF_LANES \
$TX_NUM_OF_CONVERTERS \
$TX_SAMPLES_PER_FRAME \
$TX_SAMPLE_WIDTH \
$TX_DATAPATH_WIDTH \
$TX_DMA_SAMPLE_WIDTH
ad_ip_parameter tx_mxfe_tpl_core/dac_tpl_core CONFIG.IQCORRECTION_DISABLE 0
ad_ip_instance util_upack2 util_mxfe_upack [list \
NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $TX_DMA_SAMPLE_WIDTH \
]
set dac_data_offload_size [expr $dac_data_width / 8 * 2**$dac_fifo_address_width]
ad_data_offload_create $dac_data_offload_name \
1 \
$dac_do_mem_type \
$dac_data_offload_size \
$dac_data_width \
$dac_data_width \
$do_axi_data_width \
$SHARED_DEVCLK
ad_ip_instance axi_dmac axi_mxfe_tx_dma
ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_mxfe_tx_dma CONFIG.ID 0
ad_ip_parameter axi_mxfe_tx_dma CONFIG.AXI_SLICE_SRC 1
ad_ip_parameter axi_mxfe_tx_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_mxfe_tx_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_mxfe_tx_dma CONFIG.CYCLIC 1
ad_ip_parameter axi_mxfe_tx_dma CONFIG.MAX_BYTES_PER_BURST 4096
ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr min(512, $dac_dma_data_width)]
ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width
}
# adc peripherals
adi_axi_jesd204_rx_create axi_mxfe_rx_jesd $RX_NUM_OF_LANES $RX_NUM_LINKS $ENCODER_SEL
ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.TPL_DATA_PATH_WIDTH $RX_DATAPATH_WIDTH
ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.SYSREF_IOB false
ad_ip_parameter axi_mxfe_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 1
adi_tpl_jesd204_rx_create rx_mxfe_tpl_core $RX_NUM_OF_LANES \
$RX_NUM_OF_CONVERTERS \
$RX_SAMPLES_PER_FRAME \
$RX_SAMPLE_WIDTH \
$RX_DATAPATH_WIDTH \
$RX_DMA_SAMPLE_WIDTH
ad_ip_instance util_cpack2 util_mxfe_cpack [list \
NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $RX_DMA_SAMPLE_WIDTH \
]
set adc_data_offload_size [expr $adc_data_width / 8 * 2**$adc_fifo_address_width]
ad_data_offload_create $adc_data_offload_name \
0 \
$adc_do_mem_type \
$adc_data_offload_size \
$adc_data_width \
$adc_data_width \
$do_axi_data_width \
$SHARED_DEVCLK
ad_ip_instance axi_dmac axi_mxfe_rx_dma
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_mxfe_rx_dma CONFIG.ID 0
ad_ip_parameter axi_mxfe_rx_dma CONFIG.AXI_SLICE_SRC 1
ad_ip_parameter axi_mxfe_rx_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_mxfe_rx_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_mxfe_rx_dma CONFIG.MAX_BYTES_PER_BURST 4096
ad_ip_parameter axi_mxfe_rx_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width
ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_DEST $adc_dma_data_width
# dac peripherals
adi_axi_jesd204_tx_create axi_mxfe_tx_jesd $TX_NUM_OF_LANES $TX_NUM_LINKS $ENCODER_SEL
ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.TPL_DATA_PATH_WIDTH $TX_DATAPATH_WIDTH
ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.SYSREF_IOB false
#ad_ip_parameter axi_mxfe_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1
adi_tpl_jesd204_tx_create tx_mxfe_tpl_core $TX_NUM_OF_LANES \
$TX_NUM_OF_CONVERTERS \
$TX_SAMPLES_PER_FRAME \
$TX_SAMPLE_WIDTH \
$TX_DATAPATH_WIDTH \
$TX_DMA_SAMPLE_WIDTH
ad_ip_parameter tx_mxfe_tpl_core/dac_tpl_core CONFIG.IQCORRECTION_DISABLE 0
ad_ip_instance util_upack2 util_mxfe_upack [list \
NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $TX_DMA_SAMPLE_WIDTH \
]
set dac_data_offload_size [expr $dac_data_width / 8 * 2**$dac_fifo_address_width]
ad_data_offload_create $dac_data_offload_name \
1 \
$dac_do_mem_type \
$dac_data_offload_size \
$dac_data_width \
$dac_data_width \
$do_axi_data_width \
$SHARED_DEVCLK
ad_ip_instance axi_dmac axi_mxfe_tx_dma
ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_mxfe_tx_dma CONFIG.ID 0
ad_ip_parameter axi_mxfe_tx_dma CONFIG.AXI_SLICE_SRC 1
ad_ip_parameter axi_mxfe_tx_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_mxfe_tx_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_LENGTH_WIDTH 24
ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_mxfe_tx_dma CONFIG.CYCLIC 1
ad_ip_parameter axi_mxfe_tx_dma CONFIG.MAX_BYTES_PER_BURST 4096
ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_DATA_WIDTH_SRC $dac_dma_data_width
ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width
# reference clocks & resets
create_bd_port -dir I ref_clk_q0
create_bd_port -dir I ref_clk_q1
@ -281,232 +329,250 @@ if {$ADI_PHY_SEL == 1} {
ad_xcvrpll ref_clk_q$quad_index util_mxfe_xcvr/qpll_ref_clk_$i
}
}
ad_xcvrpll axi_mxfe_tx_xcvr/up_pll_rst util_mxfe_xcvr/up_qpll_rst_*
ad_xcvrpll axi_mxfe_rx_xcvr/up_pll_rst util_mxfe_xcvr/up_cpll_rst_*
ad_connect $sys_cpu_resetn util_mxfe_xcvr/up_rstn
ad_connect $sys_cpu_clk util_mxfe_xcvr/up_clk
# connections (adc)
ad_xcvrcon util_mxfe_xcvr axi_mxfe_rx_xcvr axi_mxfe_rx_jesd {} {} rx_device_clk
# connections (dac)
ad_xcvrcon util_mxfe_xcvr axi_mxfe_tx_xcvr axi_mxfe_tx_jesd {} {} tx_device_clk
if {$INTF_CFG != "TX"} {
ad_xcvrpll axi_mxfe_rx_xcvr/up_pll_rst util_mxfe_xcvr/up_cpll_rst_*
ad_xcvrcon util_mxfe_xcvr axi_mxfe_rx_xcvr axi_mxfe_rx_jesd {} {} rx_device_clk
}
if {$INTF_CFG != "RX"} {
ad_xcvrpll axi_mxfe_tx_xcvr/up_pll_rst util_mxfe_xcvr/up_qpll_rst_*
ad_xcvrcon util_mxfe_xcvr axi_mxfe_tx_xcvr axi_mxfe_tx_jesd {} {} tx_device_clk
}
} else {
ad_connect ref_clk_q0 jesd204_phy/GT_REFCLK
if {$INTF_CFG != "TX"} {
set rx_link_clock jesd204_phy/rxusrclk_out
# Connect PHY to Link Layer
for {set j 0} {$j < $RX_NUM_OF_LANES} {incr j} {
ad_connect axi_mxfe_rx_jesd/rx_phy${j} jesd204_phy/rx${j}
}
ad_connect axi_mxfe_rx_jesd/rx_axi/device_reset jesd204_phy/reset_rx_pll_and_datapath_in
ad_connect $rx_link_clock /axi_mxfe_rx_jesd/link_clk
ad_connect rx_device_clk /axi_mxfe_rx_jesd/device_clk
set rx_link_clock jesd204_phy/rxusrclk_out
set tx_link_clock jesd204_phy/txusrclk_out
create_bd_port -dir I rx_sysref_0
ad_connect axi_mxfe_rx_jesd/sysref rx_sysref_0
# Connect PHY to Link Layer
for {set j 0} {$j < $RX_NUM_OF_LANES} {incr j} {
ad_connect axi_mxfe_tx_jesd/tx_phy${j} jesd204_phy/tx${j}
create_bd_port -dir O rx_sync_0
}
if {$INTF_CFG != "RX"} {
set tx_link_clock jesd204_phy/txusrclk_out
# Connect PHY to Link Layer
for {set j 0} {$j < $TX_NUM_OF_LANES} {incr j} {
ad_connect axi_mxfe_tx_jesd/tx_phy${j} jesd204_phy/tx${j}
}
ad_connect axi_mxfe_tx_jesd/tx_axi/device_reset jesd204_phy/reset_tx_pll_and_datapath_in
ad_connect $tx_link_clock /axi_mxfe_tx_jesd/link_clk
ad_connect tx_device_clk /axi_mxfe_tx_jesd/device_clk
ad_connect axi_mxfe_rx_jesd/rx_phy${j} jesd204_phy/rx${j}
create_bd_port -dir I tx_sysref_0
ad_connect axi_mxfe_tx_jesd/sysref tx_sysref_0
create_bd_port -dir I tx_sync_0
}
ad_connect $sys_cpu_clk jesd204_phy/apb3clk
ad_connect axi_mxfe_rx_jesd/rx_axi/device_reset jesd204_phy/reset_rx_pll_and_datapath_in
ad_connect axi_mxfe_tx_jesd/tx_axi/device_reset jesd204_phy/reset_tx_pll_and_datapath_in
ad_connect $rx_link_clock /axi_mxfe_rx_jesd/link_clk
ad_connect rx_device_clk /axi_mxfe_rx_jesd/device_clk
ad_connect $tx_link_clock /axi_mxfe_tx_jesd/link_clk
ad_connect tx_device_clk /axi_mxfe_tx_jesd/device_clk
create_bd_port -dir I rx_sysref_0
create_bd_port -dir I tx_sysref_0
ad_connect axi_mxfe_rx_jesd/sysref rx_sysref_0
ad_connect axi_mxfe_tx_jesd/sysref tx_sysref_0
create_bd_port -dir O rx_sync_0
create_bd_port -dir I tx_sync_0
}
# device clock domain
ad_connect rx_device_clk rx_mxfe_tpl_core/link_clk
ad_connect rx_device_clk util_mxfe_cpack/clk
ad_connect rx_device_clk $adc_data_offload_name/s_axis_aclk
if {$INTF_CFG != "TX"} {
# RX connections
# Device clock domain
ad_connect rx_device_clk rx_mxfe_tpl_core/link_clk
ad_connect rx_device_clk util_mxfe_cpack/clk
ad_connect rx_device_clk $adc_data_offload_name/s_axis_aclk
ad_connect tx_device_clk tx_mxfe_tpl_core/link_clk
ad_connect tx_device_clk util_mxfe_upack/clk
ad_connect tx_device_clk $dac_data_offload_name/m_axis_aclk
# Clocks
ad_connect $sys_dma_clk $adc_data_offload_name/m_axis_aclk
ad_connect $sys_dma_clk axi_mxfe_rx_dma/s_axis_aclk
# Clocks
ad_connect $sys_dma_clk $adc_data_offload_name/m_axis_aclk
ad_connect $sys_dma_clk $dac_data_offload_name/s_axis_aclk
# Resets
ad_connect rx_device_clk_rstgen/peripheral_aresetn $adc_data_offload_name/s_axis_aresetn
ad_connect $sys_dma_resetn $adc_data_offload_name/m_axis_aresetn
ad_connect $sys_dma_resetn axi_mxfe_rx_dma/m_dest_axi_aresetn
ad_connect $sys_cpu_resetn $adc_data_offload_name/s_axi_aresetn
ad_connect $sys_dma_clk axi_mxfe_rx_dma/s_axis_aclk
ad_connect $sys_dma_clk axi_mxfe_tx_dma/m_axis_aclk
ad_connect $sys_cpu_clk $dac_data_offload_name/s_axi_aclk
ad_connect $sys_cpu_clk $adc_data_offload_name/s_axi_aclk
# Link Layer to Transport Layer
ad_connect axi_mxfe_rx_jesd/rx_sof rx_mxfe_tpl_core/link_sof
ad_connect axi_mxfe_rx_jesd/rx_data_tdata rx_mxfe_tpl_core/link_data
ad_connect axi_mxfe_rx_jesd/rx_data_tvalid rx_mxfe_tpl_core/link_valid
# Resets
ad_connect rx_device_clk_rstgen/peripheral_aresetn $adc_data_offload_name/s_axis_aresetn
ad_connect $sys_dma_resetn $adc_data_offload_name/m_axis_aresetn
ad_connect tx_device_clk_rstgen/peripheral_aresetn $dac_data_offload_name/m_axis_aresetn
ad_connect $sys_dma_resetn $dac_data_offload_name/s_axis_aresetn
ad_connect $sys_dma_resetn axi_mxfe_rx_dma/m_dest_axi_aresetn
ad_connect $sys_dma_resetn axi_mxfe_tx_dma/m_src_axi_aresetn
ad_connect $sys_cpu_resetn $dac_data_offload_name/s_axi_aresetn
ad_connect $sys_cpu_resetn $adc_data_offload_name/s_axi_aresetn
#
# connect adc dataflow
#
# Connect Link Layer to Transport Layer
#
ad_connect axi_mxfe_rx_jesd/rx_sof rx_mxfe_tpl_core/link_sof
ad_connect axi_mxfe_rx_jesd/rx_data_tdata rx_mxfe_tpl_core/link_data
ad_connect axi_mxfe_rx_jesd/rx_data_tvalid rx_mxfe_tpl_core/link_valid
ad_connect rx_mxfe_tpl_core/adc_valid_0 util_mxfe_cpack/fifo_wr_en
for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
ad_connect rx_mxfe_tpl_core/adc_enable_$i util_mxfe_cpack/enable_$i
ad_connect rx_mxfe_tpl_core/adc_data_$i util_mxfe_cpack/fifo_wr_data_$i
}
ad_connect rx_mxfe_tpl_core/adc_dovf util_mxfe_cpack/fifo_wr_overflow
ad_connect util_mxfe_cpack/packed_fifo_wr_data $adc_data_offload_name/s_axis_tdata
ad_connect util_mxfe_cpack/packed_fifo_wr_en $adc_data_offload_name/s_axis_tvalid
ad_connect $adc_data_offload_name/s_axis_tlast GND
ad_connect $adc_data_offload_name/s_axis_tkeep VCC
ad_connect $adc_data_offload_name/m_axis axi_mxfe_rx_dma/s_axis
# connect dac dataflow
#
# Connect Link Layer to Transport Layer
#
ad_connect tx_mxfe_tpl_core/link axi_mxfe_tx_jesd/tx_data
ad_connect tx_mxfe_tpl_core/dac_valid_0 util_mxfe_upack/fifo_rd_en
for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
ad_connect util_mxfe_upack/fifo_rd_data_$i tx_mxfe_tpl_core/dac_data_$i
ad_connect tx_mxfe_tpl_core/dac_enable_$i util_mxfe_upack/enable_$i
}
ad_connect $dac_data_offload_name/s_axis axi_mxfe_tx_dma/m_axis
ad_connect util_mxfe_upack/s_axis $dac_data_offload_name/m_axis
ad_connect $dac_data_offload_name/init_req axi_mxfe_tx_dma/m_axis_xfer_req
ad_connect $adc_data_offload_name/init_req axi_mxfe_rx_dma/s_axis_xfer_req
ad_connect tx_mxfe_tpl_core/dac_dunf GND
# interconnect (cpu)
if {$ADI_PHY_SEL == 1} {
ad_cpu_interconnect 0x44a60000 axi_mxfe_rx_xcvr
ad_cpu_interconnect 0x44b60000 axi_mxfe_tx_xcvr
}
ad_cpu_interconnect 0x44a10000 rx_mxfe_tpl_core
ad_cpu_interconnect 0x44b10000 tx_mxfe_tpl_core
ad_cpu_interconnect 0x44a90000 axi_mxfe_rx_jesd
ad_cpu_interconnect 0x44b90000 axi_mxfe_tx_jesd
ad_cpu_interconnect 0x7c420000 axi_mxfe_rx_dma
ad_cpu_interconnect 0x7c430000 axi_mxfe_tx_dma
ad_cpu_interconnect 0x7c440000 $dac_data_offload_name
ad_cpu_interconnect 0x7c450000 $adc_data_offload_name
# Reserved for TDD! 0x7c460000
# interconnect (gt/adc)
if {$ADI_PHY_SEL == 1} {
ad_mem_hp0_interconnect $sys_cpu_clk axi_mxfe_rx_xcvr/m_axi
}
ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect $sys_dma_clk axi_mxfe_rx_dma/m_dest_axi
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_dma_clk axi_mxfe_tx_dma/m_src_axi
# interrupts
ad_cpu_interrupt ps-13 mb-12 axi_mxfe_rx_dma/irq
ad_cpu_interrupt ps-12 mb-13 axi_mxfe_tx_dma/irq
ad_cpu_interrupt ps-11 mb-14 axi_mxfe_rx_jesd/irq
ad_cpu_interrupt ps-10 mb-15 axi_mxfe_tx_jesd/irq
if {$ADI_PHY_SEL == 1} {
# Create dummy outputs for unused Tx lanes
for {set i $TX_NUM_OF_LANES} {$i < 8} {incr i} {
create_bd_port -dir O tx_data_${i}_n
create_bd_port -dir O tx_data_${i}_p
ad_connect rx_mxfe_tpl_core/adc_valid_0 util_mxfe_cpack/fifo_wr_en
for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
ad_connect rx_mxfe_tpl_core/adc_enable_$i util_mxfe_cpack/enable_$i
ad_connect rx_mxfe_tpl_core/adc_data_$i util_mxfe_cpack/fifo_wr_data_$i
}
# Create dummy outputs for unused Rx lanes
for {set i $RX_NUM_OF_LANES} {$i < 8} {incr i} {
create_bd_port -dir I rx_data_${i}_n
create_bd_port -dir I rx_data_${i}_p
ad_connect rx_mxfe_tpl_core/adc_dovf util_mxfe_cpack/fifo_wr_overflow
ad_connect util_mxfe_cpack/packed_fifo_wr_data $adc_data_offload_name/s_axis_tdata
ad_connect util_mxfe_cpack/packed_fifo_wr_en $adc_data_offload_name/s_axis_tvalid
ad_connect $adc_data_offload_name/s_axis_tlast GND
ad_connect $adc_data_offload_name/s_axis_tkeep VCC
ad_connect $adc_data_offload_name/m_axis axi_mxfe_rx_dma/s_axis
ad_connect $adc_data_offload_name/init_req axi_mxfe_rx_dma/s_axis_xfer_req
# Interconnect
# CPU
if {$ADI_PHY_SEL == 1} {
ad_cpu_interconnect 0x44a60000 axi_mxfe_rx_xcvr
}
ad_cpu_interconnect 0x44a10000 rx_mxfe_tpl_core
ad_cpu_interconnect 0x44a90000 axi_mxfe_rx_jesd
ad_cpu_interconnect 0x7c420000 axi_mxfe_rx_dma
ad_cpu_interconnect 0x7c450000 $adc_data_offload_name
# GT / ADC
if {$ADI_PHY_SEL == 1} {
ad_mem_hp0_interconnect $sys_cpu_clk axi_mxfe_rx_xcvr/m_axi
}
ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect $sys_dma_clk axi_mxfe_rx_dma/m_dest_axi
# Interrupts
ad_cpu_interrupt ps-13 mb-12 axi_mxfe_rx_dma/irq
ad_cpu_interrupt ps-11 mb-14 axi_mxfe_rx_jesd/irq
}
if {$INTF_CFG != "RX"} {
# TX connections
# Device clock domain
ad_connect tx_device_clk tx_mxfe_tpl_core/link_clk
ad_connect tx_device_clk util_mxfe_upack/clk
ad_connect tx_device_clk $dac_data_offload_name/m_axis_aclk
# Clocks
ad_connect $sys_dma_clk $dac_data_offload_name/s_axis_aclk
ad_connect $sys_dma_clk axi_mxfe_tx_dma/m_axis_aclk
# Resets
ad_connect tx_device_clk_rstgen/peripheral_aresetn $dac_data_offload_name/m_axis_aresetn
ad_connect $sys_dma_resetn $dac_data_offload_name/s_axis_aresetn
ad_connect $sys_dma_resetn axi_mxfe_tx_dma/m_src_axi_aresetn
ad_connect $sys_cpu_resetn $dac_data_offload_name/s_axi_aresetn
# Link Layer to Transport Layer
ad_connect tx_mxfe_tpl_core/link axi_mxfe_tx_jesd/tx_data
ad_connect tx_mxfe_tpl_core/dac_valid_0 util_mxfe_upack/fifo_rd_en
for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
ad_connect util_mxfe_upack/fifo_rd_data_$i tx_mxfe_tpl_core/dac_data_$i
ad_connect tx_mxfe_tpl_core/dac_enable_$i util_mxfe_upack/enable_$i
}
ad_connect $dac_data_offload_name/s_axis axi_mxfe_tx_dma/m_axis
ad_connect util_mxfe_upack/s_axis $dac_data_offload_name/m_axis
ad_connect $dac_data_offload_name/init_req axi_mxfe_tx_dma/m_axis_xfer_req
ad_connect tx_mxfe_tpl_core/dac_dunf GND
# Interconnect
if {$ADI_PHY_SEL == 1} {
# CPU
ad_cpu_interconnect 0x44b60000 axi_mxfe_tx_xcvr
}
# CPU
ad_cpu_interconnect 0x44b10000 tx_mxfe_tpl_core
ad_cpu_interconnect 0x44b90000 axi_mxfe_tx_jesd
ad_cpu_interconnect 0x7c430000 axi_mxfe_tx_dma
ad_cpu_interconnect 0x7c440000 $dac_data_offload_name
# GT / ADC
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_dma_clk axi_mxfe_tx_dma/m_src_axi
# Interrupts
ad_cpu_interrupt ps-12 mb-13 axi_mxfe_tx_dma/irq
ad_cpu_interrupt ps-10 mb-15 axi_mxfe_tx_jesd/irq
}
# Dummy outputs for unused lanes
if {$ADI_PHY_SEL == 1} {
if {$INTF_CFG != "TX"} {
# Unused Rx lanes
for {set i $RX_NUM_OF_LANES} {$i < 8} {incr i} {
create_bd_port -dir I rx_data_${i}_n
create_bd_port -dir I rx_data_${i}_p
}
}
if {$INTF_CFG != "RX"} {
# Unused Tx lanes
for {set i $TX_NUM_OF_LANES} {$i < 8} {incr i} {
create_bd_port -dir O tx_data_${i}_n
create_bd_port -dir O tx_data_${i}_p
}
}
} else {
make_bd_intf_pins_external [get_bd_intf_pins jesd204_phy/GT_Serial]
for {set j 0} {$j < $num_quads} {incr j} {
make_bd_intf_pins_external [get_bd_intf_pins jesd204_phy/GT_Serial_${j}]
}
}
#
# Sync at TPL level
#
# Sync at TPL level
create_bd_port -dir I ext_sync_in
# Enable ADC external sync
ad_ip_parameter rx_mxfe_tpl_core/adc_tpl_core CONFIG.EXT_SYNC 1
ad_connect ext_sync_in rx_mxfe_tpl_core/adc_tpl_core/adc_sync_in
if {$INTF_CFG != "TX"} {
# ADC (Rx) external sync
ad_ip_parameter rx_mxfe_tpl_core/adc_tpl_core CONFIG.EXT_SYNC 1
ad_connect ext_sync_in rx_mxfe_tpl_core/adc_tpl_core/adc_sync_in
if {$INTF_CFG == "RXTX"} {
# Rx & Tx
ad_ip_instance util_vector_logic manual_sync_or [list \
C_SIZE 1 \
C_OPERATION {or} \
]
ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_sync_manual_req_out manual_sync_or/Op1
ad_connect manual_sync_or/Res rx_mxfe_tpl_core/adc_tpl_core/adc_sync_manual_req_in
} else {
# Only Rx
ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_sync_manual_req_out rx_mxfe_tpl_core/adc_tpl_core/adc_sync_manual_req_in
}
# Reset pack cores
ad_ip_instance util_reduced_logic cpack_rst_logic
ad_ip_parameter cpack_rst_logic config.c_operation {or}
ad_ip_parameter cpack_rst_logic config.c_size {3}
# Enable DAC external sync
ad_ip_parameter tx_mxfe_tpl_core/dac_tpl_core CONFIG.EXT_SYNC 1
ad_connect ext_sync_in tx_mxfe_tpl_core/dac_tpl_core/dac_sync_in
ad_ip_instance util_vector_logic rx_do_rstout_logic
ad_ip_parameter rx_do_rstout_logic config.c_operation {not}
ad_ip_parameter rx_do_rstout_logic config.c_size {1}
ad_ip_instance util_vector_logic manual_sync_or [list \
C_SIZE 1 \
C_OPERATION {or} \
]
ad_connect $adc_data_offload_name/s_axis_tready rx_do_rstout_logic/Op1
ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_sync_manual_req_out manual_sync_or/Op1
ad_connect tx_mxfe_tpl_core/dac_tpl_core/dac_sync_manual_req_out manual_sync_or/Op2
ad_ip_instance xlconcat cpack_reset_sources
ad_ip_parameter cpack_reset_sources config.num_ports {3}
ad_connect rx_device_clk_rstgen/peripheral_reset cpack_reset_sources/in0
ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_rst cpack_reset_sources/in1
ad_connect rx_do_rstout_logic/res cpack_reset_sources/in2
ad_connect manual_sync_or/Res tx_mxfe_tpl_core/dac_tpl_core/dac_sync_manual_req_in
ad_connect manual_sync_or/Res rx_mxfe_tpl_core/adc_tpl_core/adc_sync_manual_req_in
ad_connect cpack_reset_sources/dout cpack_rst_logic/op1
ad_connect cpack_rst_logic/res util_mxfe_cpack/reset
}
if {$INTF_CFG != "RX"} {
# DAC (Tx) external sync
ad_ip_parameter tx_mxfe_tpl_core/dac_tpl_core CONFIG.EXT_SYNC 1
ad_connect ext_sync_in tx_mxfe_tpl_core/dac_tpl_core/dac_sync_in
if {$INTF_CFG == "RXTX"} {
# Rx & Tx
ad_connect tx_mxfe_tpl_core/dac_tpl_core/dac_sync_manual_req_out manual_sync_or/Op2
ad_connect manual_sync_or/Res tx_mxfe_tpl_core/dac_tpl_core/dac_sync_manual_req_in
} else {
# Only Tx
ad_connect tx_mxfe_tpl_core/dac_tpl_core/dac_sync_manual_req_out tx_mxfe_tpl_core/dac_tpl_core/dac_sync_manual_req_in
}
# Reset upack cores
ad_ip_instance util_reduced_logic upack_rst_logic
ad_ip_parameter upack_rst_logic config.c_operation {or}
ad_ip_parameter upack_rst_logic config.c_size {2}
# Reset pack cores
ad_ip_instance util_reduced_logic cpack_rst_logic
ad_ip_parameter cpack_rst_logic config.c_operation {or}
ad_ip_parameter cpack_rst_logic config.c_size {3}
ad_ip_instance xlconcat upack_reset_sources
ad_ip_parameter upack_reset_sources config.num_ports {2}
ad_connect tx_device_clk_rstgen/peripheral_reset upack_reset_sources/in0
ad_connect tx_mxfe_tpl_core/dac_tpl_core/dac_rst upack_reset_sources/in1
ad_ip_instance util_vector_logic rx_do_rstout_logic
ad_ip_parameter rx_do_rstout_logic config.c_operation {not}
ad_ip_parameter rx_do_rstout_logic config.c_size {1}
ad_connect $adc_data_offload_name/s_axis_tready rx_do_rstout_logic/Op1
ad_ip_instance xlconcat cpack_reset_sources
ad_ip_parameter cpack_reset_sources config.num_ports {3}
ad_connect rx_device_clk_rstgen/peripheral_reset cpack_reset_sources/in0
ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_rst cpack_reset_sources/in1
ad_connect rx_do_rstout_logic/res cpack_reset_sources/in2
ad_connect cpack_reset_sources/dout cpack_rst_logic/op1
ad_connect cpack_rst_logic/res util_mxfe_cpack/reset
# Reset unpack cores
ad_ip_instance util_reduced_logic upack_rst_logic
ad_ip_parameter upack_rst_logic config.c_operation {or}
ad_ip_parameter upack_rst_logic config.c_size {2}
ad_ip_instance xlconcat upack_reset_sources
ad_ip_parameter upack_reset_sources config.num_ports {2}
ad_connect tx_device_clk_rstgen/peripheral_reset upack_reset_sources/in0
ad_connect tx_mxfe_tpl_core/dac_tpl_core/dac_rst upack_reset_sources/in1
ad_connect upack_reset_sources/dout upack_rst_logic/op1
ad_connect upack_rst_logic/res util_mxfe_upack/reset
ad_connect upack_reset_sources/dout upack_rst_logic/op1
ad_connect upack_rst_logic/res util_mxfe_upack/reset
}
if {$TDD_SUPPORT} {
set TDD_CHANNEL_CNT $ad_project_params(TDD_CHANNEL_CNT)
@ -542,9 +608,11 @@ if {$TDD_SUPPORT} {
ad_connect axi_tdd_0/tdd_channel_0 $dac_data_offload_name/sync_ext
ad_connect axi_tdd_0/tdd_channel_1 $adc_data_offload_name/sync_ext
} else {
ad_connect GND $dac_data_offload_name/sync_ext
ad_connect GND $adc_data_offload_name/sync_ext
if {$INTF_CFG != "TX"} {
ad_connect GND $adc_data_offload_name/sync_ext
}
if {$INTF_CFG != "RX"} {
ad_connect GND $dac_data_offload_name/sync_ext
}
}

134
projects/ad9081_fmca_ebz/common/versal_transceiver.tcl
View File

@ -1,40 +1,52 @@
# TODO: This works only up to 4 lanes on 64B66B
proc create_versal_phy {
{ip_name versal_phy}
{num_lanes 2}
{rx_lane_rate 11.88}
{tx_lane_rate 11.88}
{ref_clock 360}
{intf_cfg RXTX}
} {
set num_quads [expr round(1.0*$num_lanes/4)]
set num_quads [expr int(round(1.0 * $num_lanes / 4))]
set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000 / 66]]
set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000 / 66]]
if {$intf_cfg == "RX"} {
set gt_direction "SIMPLEX_RX"
set no_lanes_property "CONFIG.IP_NO_OF_RX_LANES"
} elseif {$intf_cfg == "TX"} {
set gt_direction "SIMPLEX_TX"
set no_lanes_property "CONFIG.IP_NO_OF_TX_LANES"
} else {
set gt_direction "DUPLEX"
set no_lanes_property "CONFIG.IP_NO_OF_LANES"
}
create_bd_cell -type hier ${ip_name}
# Common interface
create_bd_pin -dir O ${ip_name}/rxusrclk_out -type clk
create_bd_pin -dir O ${ip_name}/txusrclk_out -type clk
if {$intf_cfg != "TX"} {
create_bd_pin -dir O ${ip_name}/rxusrclk_out -type clk
create_bd_pin -dir I ${ip_name}/reset_rx_pll_and_datapath_in
}
if {$intf_cfg != "RX"} {
create_bd_pin -dir O ${ip_name}/txusrclk_out -type clk
create_bd_pin -dir I ${ip_name}/reset_tx_pll_and_datapath_in
}
create_bd_pin -dir I ${ip_name}/GT_REFCLK -type clk
create_bd_pin -dir I ${ip_name}/apb3clk -type clk
create_bd_pin -dir I ${ip_name}/reset_rx_pll_and_datapath_in
create_bd_pin -dir I ${ip_name}/reset_tx_pll_and_datapath_in
ad_ip_instance gt_bridge_ip ${ip_name}/gt_bridge_ip_0
set_property -dict [list \
CONFIG.BYPASS_MODE {true} \
CONFIG.IP_NO_OF_LANES ${num_lanes} \
CONFIG.IP_PRESET {GTY-JESD204_64B66B} \
CONFIG.IP_GT_DIRECTION ${gt_direction} \
${no_lanes_property} ${num_lanes} \
CONFIG.IP_LR0_SETTINGS [list \
PRESET GTY-JESD204_64B66B \
INTERNAL_PRESET JESD204_64B66B \
GT_TYPE GTY \
GT_DIRECTION DUPLEX \
GT_DIRECTION $gt_direction \
TX_LINE_RATE $tx_lane_rate \
TX_PLL_TYPE LCPLL \
TX_REFCLK_FREQUENCY $ref_clock \
@ -185,60 +197,81 @@ set_property -dict [list \
] \
] [get_bd_cells ${ip_name}/gt_bridge_ip_0]
ad_ip_instance gt_quad_base ${ip_name}/gt_quad_base_0
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 ${ip_name}/GT_Serial
ad_connect ${ip_name}/gt_quad_base_0/GT_Serial ${ip_name}/GT_Serial
ad_ip_instance bufg_gt ${ip_name}/bufg_gt_rx
ad_ip_instance bufg_gt ${ip_name}/bufg_gt_tx
ad_connect ${ip_name}/gt_quad_base_0/ch0_rxoutclk ${ip_name}/bufg_gt_rx/outclk
ad_connect ${ip_name}/gt_quad_base_0/ch0_txoutclk ${ip_name}/bufg_gt_tx/outclk
ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/gt_bridge_ip_0/gt_rxusrclk
ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/gt_bridge_ip_0/gt_txusrclk
ad_connect ${ip_name}/gt_bridge_ip_0/rxusrclk_out ${ip_name}/rxusrclk_out
ad_connect ${ip_name}/gt_bridge_ip_0/txusrclk_out ${ip_name}/txusrclk_out
for {set j 0} {$j < $num_lanes} {incr j} {
ad_ip_instance jesd204_versal_gt_adapter_tx ${ip_name}/tx_adapt_${j}
ad_connect ${ip_name}/tx_adapt_${j}/TX_GT_IP_Interface ${ip_name}/gt_bridge_ip_0/GT_TX${j}_EXT
# TODO: This works only up to 4 lanes
ad_connect ${ip_name}/gt_bridge_ip_0/GT_TX${j} ${ip_name}/gt_quad_base_0/TX${j}_GT_IP_Interface
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 ${ip_name}/tx${j}
ad_connect ${ip_name}/tx${j} ${ip_name}/tx_adapt_${j}/TX
ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/tx_adapt_${j}/usr_clk
for {set j 0} {$j < $num_quads} {incr j} {
ad_ip_instance gt_quad_base ${ip_name}/gt_quad_base_${j}
set_property -dict [list \
CONFIG.PROT0_GT_DIRECTION ${gt_direction} \
] [get_bd_cells ${ip_name}/gt_quad_base_${j}]
if {$intf_cfg != "TX"} {
ad_ip_instance bufg_gt ${ip_name}/bufg_gt_rx_${j}
ad_connect ${ip_name}/gt_quad_base_${j}/ch0_rxoutclk ${ip_name}/bufg_gt_rx_${j}/outclk
}
if {$intf_cfg != "RX"} {
ad_ip_instance bufg_gt ${ip_name}/bufg_gt_tx_${j}
ad_connect ${ip_name}/gt_quad_base_${j}/ch0_txoutclk ${ip_name}/bufg_gt_tx_${j}/outclk
}
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 ${ip_name}/GT_Serial_${j}
ad_connect ${ip_name}/gt_quad_base_${j}/GT_Serial ${ip_name}/GT_Serial_${j}
}
for {set j 0} {$j < $num_lanes} {incr j} {
ad_ip_instance jesd204_versal_gt_adapter_rx ${ip_name}/rx_adapt_${j}
ad_connect ${ip_name}/rx_adapt_${j}/RX_GT_IP_Interface ${ip_name}/gt_bridge_ip_0/GT_RX${j}_EXT
if {$intf_cfg != "TX"} {
ad_connect ${ip_name}/bufg_gt_rx_0/usrclk ${ip_name}/gt_bridge_ip_0/gt_rxusrclk
ad_connect ${ip_name}/gt_bridge_ip_0/rxusrclk_out ${ip_name}/rxusrclk_out
# TODO: This works only up to 4 lanes
ad_connect ${ip_name}/gt_bridge_ip_0/GT_RX${j} ${ip_name}/gt_quad_base_0/RX${j}_GT_IP_Interface
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 ${ip_name}/rx${j}
ad_connect ${ip_name}/rx${j} ${ip_name}/rx_adapt_${j}/RX
for {set j 0} {$j < $num_lanes} {incr j} {
set quad_index [expr int($j / 4)]
set rx_index [expr $j % 4]
ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/rx_adapt_${j}/usr_clk
ad_ip_instance jesd204_versal_gt_adapter_rx ${ip_name}/rx_adapt_${j}
ad_connect ${ip_name}/rx_adapt_${j}/RX_GT_IP_Interface ${ip_name}/gt_bridge_ip_0/GT_RX${j}_EXT
ad_connect ${ip_name}/gt_bridge_ip_0/GT_RX${j} ${ip_name}/gt_quad_base_${quad_index}/RX${rx_index}_GT_IP_Interface
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 ${ip_name}/rx${j}
ad_connect ${ip_name}/rx${j} ${ip_name}/rx_adapt_${j}/RX
ad_connect ${ip_name}/bufg_gt_rx_${quad_index}/usrclk ${ip_name}/rx_adapt_${j}/usr_clk
}
# Clocks and resets
ad_connect ${ip_name}/reset_rx_pll_and_datapath_in ${ip_name}/gt_bridge_ip_0/reset_rx_pll_and_datapath_in
}
if {$intf_cfg != "RX"} {
ad_connect ${ip_name}/bufg_gt_tx_0/usrclk ${ip_name}/gt_bridge_ip_0/gt_txusrclk
ad_connect ${ip_name}/gt_bridge_ip_0/txusrclk_out ${ip_name}/txusrclk_out
for {set j 0} {$j < $num_lanes} {incr j} {
set quad_index [expr int($j / 4)]
set tx_index [expr $j % 4]
ad_ip_instance jesd204_versal_gt_adapter_tx ${ip_name}/tx_adapt_${j}
ad_connect ${ip_name}/tx_adapt_${j}/TX_GT_IP_Interface ${ip_name}/gt_bridge_ip_0/GT_TX${j}_EXT
ad_connect ${ip_name}/gt_bridge_ip_0/GT_TX${j} ${ip_name}/gt_quad_base_${quad_index}/TX${tx_index}_GT_IP_Interface
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 ${ip_name}/tx${j}
ad_connect ${ip_name}/tx${j} ${ip_name}/tx_adapt_${j}/TX
ad_connect ${ip_name}/bufg_gt_tx_${quad_index}/usrclk ${ip_name}/tx_adapt_${j}/usr_clk
}
# Clocks and resets
ad_connect ${ip_name}/reset_tx_pll_and_datapath_in ${ip_name}/gt_bridge_ip_0/reset_tx_pll_and_datapath_in
}
for {set i 0} {$i < $num_quads} {incr i} {
for {set j 0} {$j < 4} {incr j} {
ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/gt_quad_base_${i}/ch${j}_rxusrclk
ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/gt_quad_base_${i}/ch${j}_txusrclk
if {$intf_cfg != "TX"} {
ad_connect ${ip_name}/bufg_gt_rx_${i}/usrclk ${ip_name}/gt_quad_base_${i}/ch${j}_rxusrclk
}
if {$intf_cfg != "RX"} {
ad_connect ${ip_name}/bufg_gt_tx_${i}/usrclk ${ip_name}/gt_quad_base_${i}/ch${j}_txusrclk
}
}
}
# Clocks and resets
ad_connect ${ip_name}/apb3clk ${ip_name}/gt_bridge_ip_0/apb3clk
ad_connect GND ${ip_name}/gt_bridge_ip_0/gtreset_in
ad_connect ${ip_name}/reset_rx_pll_and_datapath_in ${ip_name}/gt_bridge_ip_0/reset_rx_pll_and_datapath_in
ad_connect ${ip_name}/reset_tx_pll_and_datapath_in ${ip_name}/gt_bridge_ip_0/reset_tx_pll_and_datapath_in
ad_ip_instance xlconcat ${ip_name}/xlconcat_0 [list \
NUM_PORTS $num_quads \
@ -257,4 +290,3 @@ ad_connect ${ip_name}/xlconcat_0/dout ${ip_name}/util_reduced_logic_0/Op1
ad_connect ${ip_name}/util_reduced_logic_0/Res ${ip_name}/gt_bridge_ip_0/gtpowergood
}

2
projects/ad9081_fmca_ebz/vck190/system_project.tcl
View File

@ -26,11 +26,11 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported
# [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices
# [RX/TX]_KS_PER_CHANNEL : Number of samples stored in internal buffers in kilosamples per converter (M)
#
# make JESD_MODE=64B66B RX_LANE_RATE=24.75 TX_LANE_RATE=24.75 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12
adi_project ad9081_fmca_ebz_vck190 0 [list \
INTF_CFG RXTX \
JESD_MODE [get_env_param JESD_MODE 64B66B ]\
RX_LANE_RATE [get_env_param RX_LANE_RATE 11.88 ] \
TX_LANE_RATE [get_env_param TX_LANE_RATE 11.88 ] \

153
projects/ad9081_fmca_ebz/vck190/system_top.v
View File

@ -255,56 +255,113 @@ module system_top #(
assign gpio_i[94:64] = gpio_o[94:64];
assign gpio_i[31:10] = gpio_o[31:10];
system_wrapper i_system_wrapper (
.gpio0_i (gpio_i[31:0]),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio1_i (gpio_i[63:32]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio2_i (gpio_i[95:64]),
.gpio2_o (gpio_o[95:64]),
.gpio2_t (gpio_t[95:64]),
.ddr4_dimm1_sma_clk_clk_n (sys_clk_n),
.ddr4_dimm1_sma_clk_clk_p (sys_clk_p),
.ddr4_dimm1_act_n (ddr4_act_n),
.ddr4_dimm1_adr (ddr4_adr),
.ddr4_dimm1_ba (ddr4_ba),
.ddr4_dimm1_bg (ddr4_bg),
.ddr4_dimm1_ck_c (ddr4_ck_c),
.ddr4_dimm1_ck_t (ddr4_ck_t),
.ddr4_dimm1_cke (ddr4_cke),
.ddr4_dimm1_cs_n (ddr4_cs_n),
.ddr4_dimm1_dm_n (ddr4_dm_n),
.ddr4_dimm1_dq (ddr4_dq),
.ddr4_dimm1_dqs_c (ddr4_dqs_c),
.ddr4_dimm1_dqs_t (ddr4_dqs_t),
.ddr4_dimm1_odt (ddr4_odt),
.ddr4_dimm1_reset_n (ddr4_reset_n),
.spi0_csn (spi0_csn),
.spi0_miso (spi0_miso),
.spi0_mosi (spi0_mosi),
.spi0_sclk (spi0_sclk),
.spi1_csn (spi1_csn),
.spi1_miso (spi1_miso),
.spi1_mosi (spi1_mosi),
.spi1_sclk (spi1_sclk),
// FMC HPC
// TODO: Max 4 lanes
.GT_Serial_0_gtx_p (tx_data_p_loc[3:0]),
.GT_Serial_0_gtx_n (tx_data_n_loc[3:0]),
.GT_Serial_0_grx_p (rx_data_p_loc[3:0]),
.GT_Serial_0_grx_n (rx_data_n_loc[3:0]),
generate
if (RX_JESD_L > 4 || TX_JESD_L > 4) begin
system_wrapper i_system_wrapper (
.gpio0_i (gpio_i[31:0]),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio1_i (gpio_i[63:32]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio2_i (gpio_i[95:64]),
.gpio2_o (gpio_o[95:64]),
.gpio2_t (gpio_t[95:64]),
.ddr4_dimm1_sma_clk_clk_n (sys_clk_n),
.ddr4_dimm1_sma_clk_clk_p (sys_clk_p),
.ddr4_dimm1_act_n (ddr4_act_n),
.ddr4_dimm1_adr (ddr4_adr),
.ddr4_dimm1_ba (ddr4_ba),
.ddr4_dimm1_bg (ddr4_bg),
.ddr4_dimm1_ck_c (ddr4_ck_c),
.ddr4_dimm1_ck_t (ddr4_ck_t),
.ddr4_dimm1_cke (ddr4_cke),
.ddr4_dimm1_cs_n (ddr4_cs_n),
.ddr4_dimm1_dm_n (ddr4_dm_n),
.ddr4_dimm1_dq (ddr4_dq),
.ddr4_dimm1_dqs_c (ddr4_dqs_c),
.ddr4_dimm1_dqs_t (ddr4_dqs_t),
.ddr4_dimm1_odt (ddr4_odt),
.ddr4_dimm1_reset_n (ddr4_reset_n),
.spi0_csn (spi0_csn),
.spi0_miso (spi0_miso),
.spi0_mosi (spi0_mosi),
.spi0_sclk (spi0_sclk),
.spi1_csn (spi1_csn),
.spi1_miso (spi1_miso),
.spi1_mosi (spi1_mosi),
.spi1_sclk (spi1_sclk),
// FMC HPC
.GT_Serial_0_0_gtx_p (tx_data_p_loc[3:0]),
.GT_Serial_0_0_gtx_n (tx_data_n_loc[3:0]),
.GT_Serial_0_0_grx_p (rx_data_p_loc[3:0]),
.GT_Serial_0_0_grx_n (rx_data_n_loc[3:0]),
.GT_Serial_1_0_gtx_p (tx_data_p_loc[7:4]),
.GT_Serial_1_0_gtx_n (tx_data_n_loc[7:4]),
.GT_Serial_1_0_grx_p (rx_data_p_loc[7:4]),
.GT_Serial_1_0_grx_n (rx_data_n_loc[7:4]),
.ref_clk_q0 (ref_clk),
.ref_clk_q1 (ref_clk),
.ref_clk_q0 (ref_clk),
.ref_clk_q1 (ref_clk),
.rx_device_clk (rx_device_clk),
.tx_device_clk (tx_device_clk),
.rx_sync_0 (rx_syncout),
.tx_sync_0 (tx_syncin),
.rx_sysref_0 (sysref),
.tx_sysref_0 (sysref));
.rx_device_clk (rx_device_clk),
.tx_device_clk (tx_device_clk),
.rx_sync_0 (rx_syncout),
.tx_sync_0 (tx_syncin),
.rx_sysref_0 (sysref),
.tx_sysref_0 (sysref));
end else begin
system_wrapper i_system_wrapper (
.gpio0_i (gpio_i[31:0]),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio1_i (gpio_i[63:32]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio2_i (gpio_i[95:64]),
.gpio2_o (gpio_o[95:64]),
.gpio2_t (gpio_t[95:64]),
.ddr4_dimm1_sma_clk_clk_n (sys_clk_n),
.ddr4_dimm1_sma_clk_clk_p (sys_clk_p),
.ddr4_dimm1_act_n (ddr4_act_n),
.ddr4_dimm1_adr (ddr4_adr),
.ddr4_dimm1_ba (ddr4_ba),
.ddr4_dimm1_bg (ddr4_bg),
.ddr4_dimm1_ck_c (ddr4_ck_c),
.ddr4_dimm1_ck_t (ddr4_ck_t),
.ddr4_dimm1_cke (ddr4_cke),
.ddr4_dimm1_cs_n (ddr4_cs_n),
.ddr4_dimm1_dm_n (ddr4_dm_n),
.ddr4_dimm1_dq (ddr4_dq),
.ddr4_dimm1_dqs_c (ddr4_dqs_c),
.ddr4_dimm1_dqs_t (ddr4_dqs_t),
.ddr4_dimm1_odt (ddr4_odt),
.ddr4_dimm1_reset_n (ddr4_reset_n),
.spi0_csn (spi0_csn),
.spi0_miso (spi0_miso),
.spi0_mosi (spi0_mosi),
.spi0_sclk (spi0_sclk),
.spi1_csn (spi1_csn),
.spi1_miso (spi1_miso),
.spi1_mosi (spi1_mosi),
.spi1_sclk (spi1_sclk),
// FMC HPC
.GT_Serial_0_0_gtx_p (tx_data_p_loc[3:0]),
.GT_Serial_0_0_gtx_n (tx_data_n_loc[3:0]),
.GT_Serial_0_0_grx_p (rx_data_p_loc[3:0]),
.GT_Serial_0_0_grx_n (rx_data_n_loc[3:0]),
.ref_clk_q0 (ref_clk),
.ref_clk_q1 (ref_clk),
.rx_device_clk (rx_device_clk),
.tx_device_clk (tx_device_clk),
.rx_sync_0 (rx_syncout),
.tx_sync_0 (tx_syncin),
.rx_sysref_0 (sysref),
.tx_sysref_0 (sysref));
end
endgenerate
assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0];
assign rx_data_n_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_n[RX_JESD_L*RX_NUM_LINKS-1:0];

1
projects/ad9081_fmca_ebz/vcu118/system_project.tcl
View File

@ -32,6 +32,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
#
adi_project ad9081_fmca_ebz_vcu118 0 [list \
INTF_CFG RXTX \
JESD_MODE [get_env_param JESD_MODE 8B10B ] \
RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \

1
projects/ad9081_fmca_ebz/vcu128/system_project.tcl
View File

@ -32,6 +32,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
#
adi_project ad9081_fmca_ebz_vcu128 0 [list \
INTF_CFG RXTX \
JESD_MODE [get_env_param JESD_MODE 8B10B ] \
RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \

28
projects/ad9081_fmca_ebz/zc706/system_project.tcl
View File

@ -25,24 +25,24 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# [RX/TX]_JESD_NP : Number of bits per sample
# [RX/TX]_NUM_LINKS : Number of links
#
#
# !!! For this carrier only 8B10B mode is supported !!!
#
adi_project ad9081_fmca_ebz_zc706 0 [list \
JESD_MODE 8B10B \
RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \
RX_JESD_M [get_env_param RX_JESD_M 8 ] \
RX_JESD_L [get_env_param RX_JESD_L 4 ] \
RX_JESD_S [get_env_param RX_JESD_S 1 ] \
RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \
RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \
TX_JESD_M [get_env_param TX_JESD_M 8 ] \
TX_JESD_L [get_env_param TX_JESD_L 4 ] \
TX_JESD_S [get_env_param TX_JESD_S 1 ] \
TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \
TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \
JESD_MODE 8B10B \
INTF_CFG RXTX \
RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \
RX_JESD_M [get_env_param RX_JESD_M 8 ] \
RX_JESD_L [get_env_param RX_JESD_L 4 ] \
RX_JESD_S [get_env_param RX_JESD_S 1 ] \
RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \
RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \
TX_JESD_M [get_env_param TX_JESD_M 8 ] \
TX_JESD_L [get_env_param TX_JESD_L 4 ] \
TX_JESD_S [get_env_param TX_JESD_S 1 ] \
TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \
TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \
]
adi_project_files ad9081_fmca_ebz_zc706 [list \

2
projects/ad9081_fmca_ebz/zcu102/system_project.tcl
View File

@ -24,9 +24,9 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported
# [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices
#
#
adi_project ad9081_fmca_ebz_zcu102 0 [list \
INTF_CFG RXTX \
JESD_MODE [get_env_param JESD_MODE 8B10B ] \
RX_LANE_RATE [get_env_param RX_LANE_RATE 10 ] \
TX_LANE_RATE [get_env_param TX_LANE_RATE 10 ] \