diff --git a/library/altera/axi_adxcvr/axi_adxcvr.v b/library/altera/axi_adxcvr/axi_adxcvr.v
index d5f38db9b..ff28d082b 100644
--- a/library/altera/axi_adxcvr/axi_adxcvr.v
+++ b/library/altera/axi_adxcvr/axi_adxcvr.v
@@ -42,7 +42,7 @@ module axi_adxcvr (
   // xcvr, lane-pll and ref-pll are shared
 
   output                        up_rst,
-  input                         up_ref_pll_locked,
+  input                         up_pll_locked,
   input   [(NUM_OF_LANES-1):0]  up_ready,
 
   input                         s_axi_aclk,
@@ -99,7 +99,7 @@ module axi_adxcvr (
     .NUM_OF_LANES (NUM_OF_LANES))
   i_up (
     .up_rst (up_rst),
-    .up_ref_pll_locked (up_ref_pll_locked),
+    .up_pll_locked (up_pll_locked),
     .up_ready (up_ready),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
diff --git a/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl b/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
index d59eb48b8..cdb1834a1 100644
--- a/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
+++ b/library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
@@ -76,8 +76,8 @@ add_interface_port s_axi s_axi_rready rready Input 1
 ad_alt_intf reset up_rst output 1 s_axi_clock
 set_interface_property if_up_rst associatedResetSinks s_axi_reset
 
-add_interface ref_pll_locked conduit end
-add_interface_port ref_pll_locked up_ref_pll_locked export Input 1
+add_interface core_pll_locked conduit end
+add_interface_port core_pll_locked up_pll_locked export Input 1
 
 # name changes
 
diff --git a/library/altera/axi_adxcvr/axi_adxcvr_up.v b/library/altera/axi_adxcvr/axi_adxcvr_up.v
index e9f9dbe9c..88418242f 100644
--- a/library/altera/axi_adxcvr/axi_adxcvr_up.v
+++ b/library/altera/axi_adxcvr/axi_adxcvr_up.v
@@ -42,7 +42,7 @@ module axi_adxcvr_up (
   // xcvr, lane-pll and ref-pll are shared
 
   output                        up_rst,
-  input                         up_ref_pll_locked,
+  input                         up_pll_locked,
   input   [(NUM_OF_LANES-1):0]  up_ready,
 
   // bus interface
@@ -111,7 +111,7 @@ module axi_adxcvr_up (
   assign up_rst = up_rst_cnt[3];
   assign up_ready_s = & up_status_32_s[NUM_OF_LANES:1];
   assign up_status_32_s[31:(NUM_OF_LANES+1)] = 'd0;
-  assign up_status_32_s[NUM_OF_LANES] = up_ref_pll_locked;
+  assign up_status_32_s[NUM_OF_LANES] = up_pll_locked;
   assign up_status_32_s[(NUM_OF_LANES-1):0] = up_ready;
 
   always @(negedge up_rstn or posedge up_clk) begin