zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

axi_adxcvr- ip/phy split

main
Rejeesh Kutty 2016-09-12 14:48:11 -04:00
parent 21545ee83f
commit 73ebf1225c
3 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
library/altera/axi_adxcvr/axi_adxcvr.v
View File

@ -42,7 +42,7 @@ module axi_adxcvr (
// xcvr, lane-pll and ref-pll are shared // xcvr, lane-pll and ref-pll are shared
output up_rst, output up_rst,
input up_ref_pll_locked, input up_pll_locked,
input [(NUM_OF_LANES-1):0] up_ready, input [(NUM_OF_LANES-1):0] up_ready,
input s_axi_aclk, input s_axi_aclk,
@ -99,7 +99,7 @@ module axi_adxcvr (
.NUM_OF_LANES (NUM_OF_LANES)) .NUM_OF_LANES (NUM_OF_LANES))
i_up ( i_up (
.up_rst (up_rst), .up_rst (up_rst),
.up_ref_pll_locked (up_ref_pll_locked), .up_pll_locked (up_pll_locked),
.up_ready (up_ready), .up_ready (up_ready),
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),

4
library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
View File

@ -76,8 +76,8 @@ add_interface_port s_axi s_axi_rready rready Input 1
ad_alt_intf reset up_rst output 1 s_axi_clock ad_alt_intf reset up_rst output 1 s_axi_clock
set_interface_property if_up_rst associatedResetSinks s_axi_reset set_interface_property if_up_rst associatedResetSinks s_axi_reset
add_interface ref_pll_locked conduit end add_interface core_pll_locked conduit end
add_interface_port ref_pll_locked up_ref_pll_locked export Input 1 add_interface_port core_pll_locked up_pll_locked export Input 1
# name changes # name changes

4
library/altera/axi_adxcvr/axi_adxcvr_up.v
View File

@ -42,7 +42,7 @@ module axi_adxcvr_up (
// xcvr, lane-pll and ref-pll are shared // xcvr, lane-pll and ref-pll are shared
output up_rst, output up_rst,
input up_ref_pll_locked, input up_pll_locked,
input [(NUM_OF_LANES-1):0] up_ready, input [(NUM_OF_LANES-1):0] up_ready,
// bus interface // bus interface
@ -111,7 +111,7 @@ module axi_adxcvr_up (
assign up_rst = up_rst_cnt[3]; assign up_rst = up_rst_cnt[3];
assign up_ready_s = & up_status_32_s[NUM_OF_LANES:1]; assign up_ready_s = & up_status_32_s[NUM_OF_LANES:1];
assign up_status_32_s[31:(NUM_OF_LANES+1)] = 'd0; assign up_status_32_s[31:(NUM_OF_LANES+1)] = 'd0;
assign up_status_32_s[NUM_OF_LANES] = up_ref_pll_locked; assign up_status_32_s[NUM_OF_LANES] = up_pll_locked;
assign up_status_32_s[(NUM_OF_LANES-1):0] = up_ready; assign up_status_32_s[(NUM_OF_LANES-1):0] = up_ready;
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin