data_offload: Improve external synchronization
This commit adds a new synthesis option to the design, that controls whether an internal clock domain crossing will be generated. Disabling this option allows you to use a synchronization signal that is synchronized to the write clock domain externally, and possibly shared between multiple devices. The default value retains the old behavior. Signed-off-by: David Winter <david.winter@analog.com>main
David Winter
Adrian Costina
parent
0372ce1821
commit
7423ecae14
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@ -55,7 +55,8 @@ module data_offload #(
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parameter DST_RAW_DATA_EN = 1'b0, // TBD
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parameter DST_CYCLIC_EN = 1'b0, // 1'b1 - CYCLIC mode enabled; 1'b0 - CYCLIC mode disabled
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parameter AUTO_BRINGUP = 1) (
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parameter AUTO_BRINGUP = 1,
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parameter SYNC_EXT_ADD_INTERNAL_CDC = 1) (
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// AXI4 Slave for configuration
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@ -215,8 +216,10 @@ module data_offload #(
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.WR_ADDRESS_WIDTH (SRC_ADDR_WIDTH),
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.WR_DATA_WIDTH (SRC_DATA_WIDTH),
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.RD_ADDRESS_WIDTH (DST_ADDR_WIDTH),
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.RD_DATA_WIDTH (DST_DATA_WIDTH))
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.RD_DATA_WIDTH (DST_DATA_WIDTH),
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.SYNC_EXT_ADD_INTERNAL_CDC (SYNC_EXT_ADD_INTERNAL_CDC ))
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i_data_offload_fsm (
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.up_clk (up_clk),
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.wr_clk (src_clk),
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.wr_resetn_in (src_rstn),
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.wr_resetn_out (fifo_src_resetn),
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@ -5,6 +5,7 @@
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<: setFileProcessingOrder late :>
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<: set mem_type [getBooleanValue "MEM_TYPE"] :>
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<: set tx_enable [getBooleanValue "TX_OR_RXN_PATH"] :>
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<: set internal_cdc [getBooleanValue "SYNC_EXT_ADD_INTERNAL_CDC"] :>
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## for all synchronization registers from util_cdc modules
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set_property ASYNC_REG TRUE \
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@ -14,8 +15,22 @@ set_property ASYNC_REG TRUE \
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## For RX in case of BRAMs
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<: if { $tx_enable == 0 } { :>
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set_false_path \
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<: if { $internal_cdc } { :>
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set_false_path \
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-to [get_pins -hierarchical * -filter {NAME=~*/i_sync_wr_sync/cdc_sync_stage1_reg[*]/D}]
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<: } :>
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/cdc_hold_reg[*]}] \
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-to [get_cells -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/out_data_reg[*]}]
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set_false_path \
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-from [get_pins -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/in_toggle_d1_reg/C}] \
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-to [get_pins -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/i_sync_out/cdc_sync_stage1_reg[*]/D}]
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set_false_path \
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-from [get_pins -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/out_toggle_d1_reg/C}] \
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-to [get_pins -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/i_sync_in/cdc_sync_stage1_reg[*]/D}]
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<: if { !$mem_type } { :>
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@ -34,8 +49,11 @@ set_false_path \
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## For TX in case of BRAMs
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<: if { $tx_enable == 1 } { :>
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<: if { $internal_cdc } { :>
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set_false_path \
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-to [get_pins -hierarchical * -filter {NAME=~*/i_sync_rd_sync/cdc_sync_stage1_reg[*]/D}]
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<: } :>
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<: if { !$mem_type } { :>
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@ -55,18 +73,6 @@ set_false_path \
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<: if { $mem_type == 1 } { :>
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set_false_path \
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-from [get_cells -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/cdc_hold_reg[*]}] \
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-to [get_cells -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/out_data_reg[*]}]
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set_false_path \
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-from [get_pins -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/in_toggle_d1_reg/C}] \
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-to [get_pins -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/i_sync_out/cdc_sync_stage1_reg[*]/D}]
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set_false_path \
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-from [get_pins -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/out_toggle_d1_reg/C}] \
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-to [get_pins -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/i_sync_in/cdc_sync_stage1_reg[*]/D}]
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set_false_path \
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-to [get_pins -hierarchical * -filter {NAME=~*i_ddr_calib_done_sync/cdc_sync_stage1_reg[0]/D}]
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@ -44,7 +44,10 @@ module data_offload_fsm #(
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parameter WR_ADDRESS_WIDTH = 4,
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parameter WR_DATA_WIDTH = 128,
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parameter RD_ADDRESS_WIDTH = 4,
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parameter RD_DATA_WIDTH = 128)(
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parameter RD_DATA_WIDTH = 128,
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parameter SYNC_EXT_ADD_INTERNAL_CDC = 1) (
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input up_clk,
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// write control interface
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input wr_clk,
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@ -132,8 +135,6 @@ module data_offload_fsm #(
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wire rd_init_ack_s;
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wire [WR_ADDRESS_WIDTH-1:0] rd_wr_last_addr_s;
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wire [WR_DATA_WIDTH/8-1:0] rd_wr_last_tkeep_s;
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wire wr_sync_internal_s;
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wire rd_sync_internal_s;
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wire wr_sync_external_s;
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wire rd_sync_external_s;
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wire wr_oneshot;
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@ -171,7 +172,7 @@ module data_offload_fsm #(
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end
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end
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SOFTWARE: begin
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if (wr_sync_internal_s) begin
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if (sync_internal) begin
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wr_fsm_state <= WR_WRITE_TO_MEM;
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end
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end
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@ -315,7 +316,7 @@ module data_offload_fsm #(
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end
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end
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SOFTWARE: begin
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if (rd_sync_internal_s) begin
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if (sync_internal) begin
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rd_fsm_state <= RD_READ_FROM_MEM;
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end
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end
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@ -555,24 +556,27 @@ module data_offload_fsm #(
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end
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end
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// When SYNC_EXT_ADD_INTERNAL_CDC is deasserted, one of these signals will end
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// up being synchronized to the "wrong" clock domain. This shouldn't matter
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// because the incorrectly synchronized signal is guarded by a synthesis constant.
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sync_bits #(
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.NUM_OF_BITS (2),
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.ASYNC_CLK (1))
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.NUM_OF_BITS (1),
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.ASYNC_CLK (SYNC_EXT_ADD_INTERNAL_CDC))
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i_sync_wr_sync (
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.in_bits ({ sync_internal, sync_external }),
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.in_bits ({ sync_external }),
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.out_clk (wr_clk),
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.out_resetn (1'b1),
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.out_bits ({ wr_sync_internal_s, wr_sync_external_s })
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.out_bits ({ wr_sync_external_s })
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);
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sync_bits #(
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.NUM_OF_BITS (2),
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.ASYNC_CLK (1))
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.NUM_OF_BITS (1),
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.ASYNC_CLK (SYNC_EXT_ADD_INTERNAL_CDC))
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i_sync_rd_sync (
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.in_bits ({ sync_internal, sync_external }),
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.in_bits ({ sync_external }),
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.out_clk (rd_clk),
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.out_resetn (1'b1),
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.out_bits ({ rd_sync_internal_s, rd_sync_external_s })
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.out_bits ({ rd_sync_external_s })
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);
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endmodule
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@ -105,6 +105,7 @@ foreach {k v} { \
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"SRC_RAW_DATA_EN" "false" \
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"DST_RAW_DATA_EN" "false" \
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"DST_CYCLIC_EN" "true" \
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"SYNC_EXT_ADD_INTERNAL_CDC" "true" \
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} { \
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set_property -dict [list \
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"value_format" "bool" \
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@ -229,6 +230,11 @@ set_property -dict [list \
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] [ipgui::get_guiparamspec -name "DST_CYCLIC_EN" -component $cc]
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set_property enablement_tcl_expr {$TX_OR_RXN_PATH == 1} [ipx::get_user_parameters DST_CYCLIC_EN -of_objects $cc]
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ipgui::add_param -name "SYNC_EXT_ADD_INTERNAL_CDC" -component $cc -parent $features_group
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set_property -dict [list \
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"display_name" "Generate CDC Circuit for sync_ext" \
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] [ipgui::get_guiparamspec -name "SYNC_EXT_ADD_INTERNAL_CDC" -component $cc]
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## Create and save the XGUI file
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ipx::create_xgui_files $cc
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@ -1,5 +1,13 @@
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proc ad_data_offload_create {instance_name datapath_type mem_type mem_size source_dwidth destination_dwidth {ddr_data_width 0} {ddr_addr_width 0}} {
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proc ad_data_offload_create {instance_name
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datapath_type
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mem_type
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mem_size
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source_dwidth
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destination_dwidth
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{ddr_data_width 0}
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{ddr_addr_width 0}
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{shared_devclk 0}} {
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global ad_hdl_dir
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global sys_cpu_resetn
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@ -44,6 +52,7 @@ proc ad_data_offload_create {instance_name datapath_type mem_type mem_size sourc
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DST_DATA_WIDTH $destination_dwidth \
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DST_ADDR_WIDTH $destination_awidth \
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DST_CYCLIC_EN $datapath_type \
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SYNC_EXT_ADD_INTERNAL_CDC [expr {!$shared_devclk}] \
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]
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if {$mem_type == 0} {
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