ad6676evb: 2014.4 updates
Rejeesh Kutty
parent
08a773b92d
commit
7456ca67a8
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@ -1,47 +1,28 @@
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# ad6676
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set spi_csn_o [create_bd_port -dir O spi_csn_o]
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set spi_csn_i [create_bd_port -dir I spi_csn_i]
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set spi_clk_i [create_bd_port -dir I spi_clk_i]
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set spi_clk_o [create_bd_port -dir O spi_clk_o]
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set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
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set spi_sdo_o [create_bd_port -dir O spi_sdo_o]
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set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
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create_bd_port -dir I rx_ref_clk
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create_bd_port -dir O rx_sync
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create_bd_port -dir O rx_sysref
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create_bd_port -dir I -from 1 -to 0 rx_data_p
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create_bd_port -dir I -from 1 -to 0 rx_data_n
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set rx_ref_clk [create_bd_port -dir I rx_ref_clk]
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set rx_sync [create_bd_port -dir O rx_sync]
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set rx_sysref [create_bd_port -dir O rx_sysref]
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set rx_data_p [create_bd_port -dir I -from 1 -to 0 rx_data_p]
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set rx_data_n [create_bd_port -dir I -from 1 -to 0 rx_data_n]
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set adc_clk [create_bd_port -dir O adc_clk]
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set adc_enable_a [create_bd_port -dir O adc_enable_a]
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set adc_valid_a [create_bd_port -dir O adc_valid_a]
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set adc_data_a [create_bd_port -dir O -from 31 -to 0 adc_data_a]
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set adc_enable_b [create_bd_port -dir O adc_enable_b]
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set adc_valid_b [create_bd_port -dir O adc_valid_b]
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set adc_data_b [create_bd_port -dir O -from 31 -to 0 adc_data_b]
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set dma_wr [create_bd_port -dir I dma_wr]
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set dma_sync [create_bd_port -dir I dma_sync]
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set dma_data [create_bd_port -dir I -from 63 -to 0 dma_data]
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set ad6676_spi_intr [create_bd_port -dir O ad6676_spi_intr]
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set ad6676_gpio_intr [create_bd_port -dir O ad6676_gpio_intr]
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set ad6676_dma_intr [create_bd_port -dir O ad6676_dma_intr]
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if {$sys_zynq == 0} {
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set gpio_ctl_i [create_bd_port -dir I -from 4 -to 0 gpio_ctl_i]
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set gpio_ctl_o [create_bd_port -dir O -from 4 -to 0 gpio_ctl_o]
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set gpio_ctl_t [create_bd_port -dir O -from 4 -to 0 gpio_ctl_t]
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}
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create_bd_port -dir O adc_clk
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create_bd_port -dir O adc_enable_a
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create_bd_port -dir O adc_valid_a
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create_bd_port -dir O -from 31 -to 0 adc_data_a
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create_bd_port -dir O adc_enable_b
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create_bd_port -dir O adc_valid_b
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create_bd_port -dir O -from 31 -to 0 adc_data_b
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create_bd_port -dir I adc_dwr
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create_bd_port -dir I adc_dsync
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create_bd_port -dir I -from 63 -to 0 adc_ddata
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# adc peripherals
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set axi_ad6676_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad6676:1.0 axi_ad6676_core]
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set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad6676_jesd]
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set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad6676_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad6676_jesd
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set_property -dict [list CONFIG.C_LANES {2}] $axi_ad6676_jesd
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@ -69,271 +50,96 @@ set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad6676_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad6676_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad6676_dma
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if {$sys_zynq == 1} {
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set axi_ad6676_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad6676_gt_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad6676_gt_interconnect
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set axi_ad6676_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad6676_dma_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad6676_dma_interconnect
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}
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# gpio and spi
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if {$sys_zynq == 0} {
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set axi_ad6676_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_ad6676_spi]
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set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_ad6676_spi
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set_property -dict [list CONFIG.C_NUM_SS_BITS {1}] $axi_ad6676_spi
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set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_ad6676_spi
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set axi_ad6676_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_ad6676_gpio]
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set_property -dict [list CONFIG.C_GPIO_WIDTH {10}] $axi_ad6676_gpio
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set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_ad6676_gpio
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}
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# additions to default configuration
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if {$sys_zynq == 1} {
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set_property -dict [list CONFIG.NUM_MI {11}] $axi_cpu_interconnect
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {42}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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set_property LEFT 41 [get_bd_ports GPIO_I]
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set_property LEFT 41 [get_bd_ports GPIO_O]
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set_property LEFT 41 [get_bd_ports GPIO_T]
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} else {
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set_property -dict [list CONFIG.NUM_MI {13}] $axi_cpu_interconnect
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set_property -dict [list CONFIG.NUM_SI {10}] $axi_mem_interconnect
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set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc
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}
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# connections (spi and gpio)
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if {$sys_zynq == 1} {
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connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
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connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_ps7/SPI0_SS_O]
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connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
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connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
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connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
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connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
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connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
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} else {
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connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_ad6676_spi/ss_i]
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connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_ad6676_spi/ss_o]
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connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_ad6676_spi/sck_i]
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connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_ad6676_spi/sck_o]
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connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_ad6676_spi/io0_i]
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connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_ad6676_spi/io0_o]
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connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_ad6676_spi/io1_i]
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}
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if {$sys_zynq == 0} {
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connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_ad6676_gpio/gpio_io_i]
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connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_ad6676_gpio/gpio_io_o]
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connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_ad6676_gpio/gpio_io_t]
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}
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# connections (gt)
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connect_bd_net -net axi_ad6676_gt_ref_clk_c [get_bd_pins axi_ad6676_gt/ref_clk_c] [get_bd_ports rx_ref_clk]
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connect_bd_net -net axi_ad6676_gt_rx_data_p [get_bd_pins axi_ad6676_gt/rx_data_p] [get_bd_ports rx_data_p]
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connect_bd_net -net axi_ad6676_gt_rx_data_n [get_bd_pins axi_ad6676_gt/rx_data_n] [get_bd_ports rx_data_n]
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connect_bd_net -net axi_ad6676_gt_rx_sync [get_bd_pins axi_ad6676_gt/rx_sync] [get_bd_ports rx_sync]
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connect_bd_net -net axi_ad6676_gt_rx_sysref [get_bd_pins axi_ad6676_gt/rx_sysref] [get_bd_ports rx_sysref]
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ad_connect axi_ad6676_gt/ref_clk_c rx_ref_clk
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ad_connect axi_ad6676_gt/rx_data_p rx_data_p
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ad_connect axi_ad6676_gt/rx_data_n rx_data_n
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ad_connect axi_ad6676_gt/rx_sync rx_sync
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ad_connect axi_ad6676_gt/rx_sysref rx_sysref
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# connections (adc)
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connect_bd_net -net axi_ad6676_gt_rx_clk [get_bd_pins axi_ad6676_gt/rx_clk_g]
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connect_bd_net -net axi_ad6676_gt_rx_clk [get_bd_pins axi_ad6676_gt/rx_clk]
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connect_bd_net -net axi_ad6676_gt_rx_clk [get_bd_pins axi_ad6676_core/rx_clk]
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connect_bd_net -net axi_ad6676_gt_rx_clk [get_bd_pins axi_ad6676_jesd/rx_core_clk]
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connect_bd_net -net axi_ad6676_gt_rx_clk [get_bd_ports adc_clk]
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connect_bd_net -net axi_ad6676_gt_rx_rst [get_bd_pins axi_ad6676_gt/rx_rst]
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connect_bd_net -net axi_ad6676_gt_rx_rst [get_bd_pins axi_ad6676_jesd/rx_reset]
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ad_connect ad6676_clk axi_ad6676_gt/rx_clk_g
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ad_connect ad6676_clk adc_clk
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ad_connect ad6676_clk axi_ad6676_gt/rx_clk
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ad_connect ad6676_clk axi_ad6676_core/rx_clk
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ad_connect ad6676_clk axi_ad6676_jesd/rx_core_clk
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ad_connect ad6676_clk axi_ad6676_dma/fifo_wr_clk
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ad_connect axi_ad6676_gt/rx_rst axi_ad6676_jesd/rx_reset
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ad_connect axi_ad6676_gt/rx_sysref axi_ad6676_jesd/rx_sysref
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ad_connect axi_ad6676_gt/tx_clk_g axi_ad6676_gt/tx_clk
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connect_bd_net -net axi_ad6676_gt_rx_sysref [get_bd_pins axi_ad6676_jesd/rx_sysref]
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connect_bd_net -net axi_ad6676_gt_rx_gt_charisk [get_bd_pins axi_ad6676_gt/rx_gt_charisk] [get_bd_pins axi_ad6676_jesd/gt_rxcharisk_in]
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connect_bd_net -net axi_ad6676_gt_rx_gt_disperr [get_bd_pins axi_ad6676_gt/rx_gt_disperr] [get_bd_pins axi_ad6676_jesd/gt_rxdisperr_in]
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connect_bd_net -net axi_ad6676_gt_rx_gt_notintable [get_bd_pins axi_ad6676_gt/rx_gt_notintable] [get_bd_pins axi_ad6676_jesd/gt_rxnotintable_in]
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connect_bd_net -net axi_ad6676_gt_rx_gt_data [get_bd_pins axi_ad6676_gt/rx_gt_data] [get_bd_pins axi_ad6676_jesd/gt_rxdata_in]
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connect_bd_net -net axi_ad6676_gt_rx_rst_done [get_bd_pins axi_ad6676_gt/rx_rst_done] [get_bd_pins axi_ad6676_jesd/rx_reset_done]
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connect_bd_net -net axi_ad6676_gt_rx_ip_comma_align [get_bd_pins axi_ad6676_gt/rx_ip_comma_align] [get_bd_pins axi_ad6676_jesd/rxencommaalign_out]
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connect_bd_net -net axi_ad6676_gt_rx_ip_sync [get_bd_pins axi_ad6676_gt/rx_ip_sync] [get_bd_pins axi_ad6676_jesd/rx_sync]
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connect_bd_net -net axi_ad6676_gt_rx_ip_sof [get_bd_pins axi_ad6676_gt/rx_ip_sof] [get_bd_pins axi_ad6676_jesd/rx_start_of_frame]
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connect_bd_net -net axi_ad6676_gt_rx_ip_data [get_bd_pins axi_ad6676_gt/rx_ip_data] [get_bd_pins axi_ad6676_jesd/rx_tdata]
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connect_bd_net -net axi_ad6676_gt_rx_data [get_bd_pins axi_ad6676_gt/rx_data] [get_bd_pins axi_ad6676_core/rx_data]
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connect_bd_net -net axi_ad6676_adc_clk [get_bd_pins axi_ad6676_core/adc_clk] [get_bd_pins axi_ad6676_dma/fifo_wr_clk]
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connect_bd_net -net axi_ad6676_adc_enable_a [get_bd_pins axi_ad6676_core/adc_enable_a] [get_bd_ports adc_enable_a]
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connect_bd_net -net axi_ad6676_adc_valid_a [get_bd_pins axi_ad6676_core/adc_valid_a] [get_bd_ports adc_valid_a]
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connect_bd_net -net axi_ad6676_adc_data_a [get_bd_pins axi_ad6676_core/adc_data_a] [get_bd_ports adc_data_a]
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connect_bd_net -net axi_ad6676_adc_enable_b [get_bd_pins axi_ad6676_core/adc_enable_b] [get_bd_ports adc_enable_b]
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connect_bd_net -net axi_ad6676_adc_valid_b [get_bd_pins axi_ad6676_core/adc_valid_b] [get_bd_ports adc_valid_b]
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connect_bd_net -net axi_ad6676_adc_data_b [get_bd_pins axi_ad6676_core/adc_data_b] [get_bd_ports adc_data_b]
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connect_bd_net -net axi_ad6676_dma_wr [get_bd_pins axi_ad6676_dma/fifo_wr_en] [get_bd_ports dma_wr]
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connect_bd_net -net axi_ad6676_dma_sync [get_bd_pins axi_ad6676_dma/fifo_wr_sync] [get_bd_ports dma_sync]
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connect_bd_net -net axi_ad6676_dma_data [get_bd_pins axi_ad6676_dma/fifo_wr_din] [get_bd_ports dma_data]
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connect_bd_net -net axi_ad6676_adc_dovf [get_bd_pins axi_ad6676_core/adc_dovf] [get_bd_pins axi_ad6676_dma/fifo_wr_overflow]
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connect_bd_net -net axi_ad6676_dma_intr [get_bd_pins axi_ad6676_dma/irq] [get_bd_ports ad6676_dma_intr]
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk
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set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_charisk]
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set_property -dict [list CONFIG.CH_CNT {2}] [get_bd_cells util_bsplit_rx_gt_charisk]
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ad_connect util_bsplit_rx_gt_charisk/data axi_ad6676_gt/rx_gt_charisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_ad6676_jesd/gt0_rxcharisk
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ad_connect util_bsplit_rx_gt_charisk/split_data_1 axi_ad6676_jesd/gt1_rxcharisk
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_disperr
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set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_disperr]
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set_property -dict [list CONFIG.CH_CNT {2}] [get_bd_cells util_bsplit_rx_gt_disperr]
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ad_connect util_bsplit_rx_gt_disperr/data axi_ad6676_gt/rx_gt_disperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_0 axi_ad6676_jesd/gt0_rxdisperr
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ad_connect util_bsplit_rx_gt_disperr/split_data_1 axi_ad6676_jesd/gt1_rxdisperr
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable
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set_property -dict [list CONFIG.CH_DW {4}] [get_bd_cells util_bsplit_rx_gt_notintable]
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set_property -dict [list CONFIG.CH_CNT {2}] [get_bd_cells util_bsplit_rx_gt_notintable]
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ad_connect util_bsplit_rx_gt_notintable/data axi_ad6676_gt/rx_gt_notintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_ad6676_jesd/gt0_rxnotintable
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ad_connect util_bsplit_rx_gt_notintable/split_data_1 axi_ad6676_jesd/gt1_rxnotintable
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create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data
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set_property -dict [list CONFIG.CH_DW {32}] [get_bd_cells util_bsplit_rx_gt_data]
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set_property -dict [list CONFIG.CH_CNT {2}] [get_bd_cells util_bsplit_rx_gt_data]
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ad_connect util_bsplit_rx_gt_data/data axi_ad6676_gt/rx_gt_data
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ad_connect util_bsplit_rx_gt_data/split_data_0 axi_ad6676_jesd/gt0_rxdata
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ad_connect util_bsplit_rx_gt_data/split_data_1 axi_ad6676_jesd/gt1_rxdata
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ad_connect axi_ad6676_gt/rx_rst_done axi_ad6676_jesd/rx_reset_done
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ad_connect axi_ad6676_gt/rx_ip_comma_align axi_ad6676_jesd/rxencommaalign_out
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ad_connect axi_ad6676_gt/rx_ip_sync axi_ad6676_jesd/rx_sync
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ad_connect axi_ad6676_gt/rx_ip_sof axi_ad6676_jesd/rx_start_of_frame
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ad_connect axi_ad6676_gt/rx_ip_data axi_ad6676_jesd/rx_tdata
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ad_connect axi_ad6676_gt/rx_data axi_ad6676_core/rx_data
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ad_connect axi_ad6676_core/adc_enable_a adc_enable_a
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ad_connect axi_ad6676_core/adc_valid_a adc_valid_a
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ad_connect axi_ad6676_core/adc_data_a adc_data_a
|
||||
ad_connect axi_ad6676_core/adc_enable_b adc_enable_b
|
||||
ad_connect axi_ad6676_core/adc_valid_b adc_valid_b
|
||||
ad_connect axi_ad6676_core/adc_data_b adc_data_b
|
||||
ad_connect axi_ad6676_dma/fifo_wr_en adc_dwr
|
||||
ad_connect axi_ad6676_dma/fifo_wr_sync adc_dsync
|
||||
ad_connect axi_ad6676_dma/fifo_wr_din adc_ddata
|
||||
ad_connect axi_ad6676_core/adc_dovf axi_ad6676_dma/fifo_wr_overflow
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad6676_dma/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad6676_core/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad6676_jesd/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad6676_gt/s_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_gt/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_core/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_jesd/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_dma/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_gt/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_core/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_jesd/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_dma/s_axi_aresetn]
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad6676_spi/axi_lite]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad6676_gpio/s_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_spi/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_spi/ext_spi_clk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_gpio/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_spi/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_gpio/s_axi_aresetn]
|
||||
|
||||
connect_bd_net -net axi_ad6676_spi_intr [get_bd_pins axi_ad6676_spi/ip2intc_irpt] [get_bd_pins ad6676_spi_intr]
|
||||
connect_bd_net -net axi_ad6676_gpio_intr [get_bd_pins axi_ad6676_gpio/ip2intc_irpt] [get_bd_pins ad6676_gpio_intr]
|
||||
}
|
||||
ad_cpu_interconnect 0x44A60000 axi_ad6676_gt
|
||||
ad_cpu_interconnect 0x44A10000 axi_ad6676_core
|
||||
ad_cpu_interconnect 0x44A91000 axi_ad6676_jesd
|
||||
ad_cpu_interconnect 0x7c420000 axi_ad6676_dma
|
||||
|
||||
# gt uses hp3, and 100MHz clock for both DRP and AXI4
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
|
||||
ad_mem_hp3_interconnect sys_cpu_clk axi_ad6676_gt/m_axi
|
||||
ad_connect sys_cpu_resetn axi_ad6676_gt/m_axi_aresetn
|
||||
ad_connect sys_cpu_clk axi_ad6676_gt/drp_clk
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad6676_gt/m_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_gt/m_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_gt/drp_clk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_gt/m_axi_aresetn]
|
||||
# interconnect (adc)
|
||||
|
||||
} else {
|
||||
ad_mem_hp2_interconnect ad6676_clk sys_ps7/S_AXI_HP2
|
||||
ad_mem_hp2_interconnect ad6676_clk axi_ad6676_dma/m_dest_axi
|
||||
ad_connect sys_cpu_resetn axi_ad6676_dma/m_dest_axi_aresetn
|
||||
|
||||
connect_bd_intf_net -intf_net axi_ad6676_gt_interconnect_m00_axi [get_bd_intf_pins axi_ad6676_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3]
|
||||
connect_bd_intf_net -intf_net axi_ad6676_gt_interconnect_s00_axi [get_bd_intf_pins axi_ad6676_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_ad6676_gt/m_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_gt_interconnect/ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_gt_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_gt_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_gt/m_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad6676_gt/drp_clk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_gt_interconnect/ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_gt/m_axi_aresetn]
|
||||
}
|
||||
# interrupts
|
||||
|
||||
# memory interconnects share the same clock (fclk2)
|
||||
|
||||
if {$sys_zynq == 1} {
|
||||
|
||||
set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
|
||||
set sys_fmc_dma_resetn_source [get_bd_pins sys_ps7/FCLK_RESET2_N]
|
||||
|
||||
connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source
|
||||
}
|
||||
|
||||
# interconnect (mem/dac)
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
|
||||
connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad6676_dma/m_dest_axi]
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad6676_dma/m_dest_axi_aclk]
|
||||
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source
|
||||
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad6676_dma/m_dest_axi_aresetn]
|
||||
|
||||
} else {
|
||||
|
||||
connect_bd_intf_net -intf_net axi_ad6676_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad6676_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
|
||||
connect_bd_intf_net -intf_net axi_ad6676_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad6676_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad6676_dma/m_dest_axi]
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad6676_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad6676_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad6676_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
|
||||
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad6676_dma/m_dest_axi_aclk]
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad6676_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad6676_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad6676_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
|
||||
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad6676_dma/m_dest_axi_aresetn]
|
||||
}
|
||||
|
||||
# ila
|
||||
|
||||
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {170}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {4}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE3_WIDTH {32}] $ila_jesd_rx_mon
|
||||
set_property -dict [list CONFIG.C_PROBE4_WIDTH {32}] $ila_jesd_rx_mon
|
||||
|
||||
connect_bd_net -net axi_ad6676_gt_rx_mon_data [get_bd_pins axi_ad6676_gt/rx_mon_data]
|
||||
connect_bd_net -net axi_ad6676_gt_rx_mon_trigger [get_bd_pins axi_ad6676_gt/rx_mon_trigger]
|
||||
connect_bd_net -net axi_ad6676_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
|
||||
connect_bd_net -net axi_ad6676_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
|
||||
connect_bd_net -net axi_ad6676_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
|
||||
connect_bd_net -net axi_ad6676_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2]
|
||||
connect_bd_net -net axi_ad6676_adc_data_a [get_bd_pins ila_jesd_rx_mon/PROBE3]
|
||||
connect_bd_net -net axi_ad6676_adc_data_b [get_bd_pins ila_jesd_rx_mon/PROBE4]
|
||||
|
||||
# address map
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad6676_core/s_axi/axi_lite] SEG_data_ad6676_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad6676_dma/s_axi/axi_lite] SEG_data_ad6676_dma
|
||||
create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad6676_jesd/s_axi/Reg] SEG_data_ad6676_jesd
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad6676_gt/s_axi/axi_lite] SEG_data_ad6676_gt
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad6676_spi/axi_lite/Reg] SEG_data_ad6676_spi
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad6676_gpio/S_AXI/Reg] SEG_data_ad6676_gpio
|
||||
}
|
||||
|
||||
if {$sys_zynq == 0} {
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad6676_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad6676_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
|
||||
|
||||
} else {
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad6676_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad6676_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm
|
||||
}
|
||||
ad_cpu_interrupt ps-13 mb-13 axi_ad6676_dma/irq
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue