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adrv9026: Initial design 

Signed-off-by: AndrDragomir <andrei.dragomir@analog.com>
main
AndrDragomir 2023-04-21 11:52:48 +03:00 committed by AndrDragomir
parent a31eb76366
commit 74a190d8b2
8 changed files with 763 additions and 0 deletions
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###############################################################################
## Copyright (C) 2018-2024 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
###############################################################################
include ../scripts/project-toplevel.mk

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projects/adrv9026/common/adrv9026_bd.tcl Normal file
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###############################################################################
## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# TX parameters
set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L) ; # L
set TX_NUM_OF_CONVERTERS $ad_project_params(TX_JESD_M) ; # M
set TX_SAMPLES_PER_FRAME $ad_project_params(TX_JESD_S) ; # S
set TX_SAMPLE_WIDTH 16 ; # N/NP
set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
# RX parameters
set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L) ; # L
set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M) ; # M
set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S) ; # S
set RX_SAMPLE_WIDTH 16 ; # N/NP
set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
set dac_fifo_name axi_adrv9026_dacfifo
set dac_data_width [expr 32*$TX_NUM_OF_LANES]
set dac_dma_data_width 128
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
# adrv9026
create_bd_port -dir I dac_fifo_bypass
create_bd_port -dir I core_clk
# dac peripherals
ad_ip_instance axi_adxcvr axi_adrv9026_tx_xcvr
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.TX_OR_RX_N 1
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.SYS_CLK_SEL 3
ad_ip_parameter axi_adrv9026_tx_xcvr CONFIG.OUT_CLK_SEL 3
adi_axi_jesd204_tx_create axi_adrv9026_tx_jesd $TX_NUM_OF_LANES
ad_ip_instance util_upack2 util_adrv9026_tx_upack [list \
NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
]
adi_tpl_jesd204_tx_create tx_adrv9026_tpl_core $TX_NUM_OF_LANES \
$TX_NUM_OF_CONVERTERS \
$TX_SAMPLES_PER_FRAME \
$TX_SAMPLE_WIDTH
ad_ip_instance axi_dmac axi_adrv9026_tx_dma
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.CYCLIC 1
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.MAX_BYTES_PER_BURST 256
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
ad_ip_parameter axi_adrv9026_tx_dma CONFIG.FIFO_SIZE 32
ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
# adc peripherals
ad_ip_instance axi_adxcvr axi_adrv9026_rx_xcvr
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.SYS_CLK_SEL 0
ad_ip_parameter axi_adrv9026_rx_xcvr CONFIG.OUT_CLK_SEL 3
adi_axi_jesd204_rx_create axi_adrv9026_rx_jesd $RX_NUM_OF_LANES
ad_ip_instance util_cpack2 util_adrv9026_rx_cpack [list \
NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
]
adi_tpl_jesd204_rx_create rx_adrv9026_tpl_core $RX_NUM_OF_LANES \
$RX_NUM_OF_CONVERTERS \
$RX_SAMPLES_PER_FRAME \
$RX_SAMPLE_WIDTH
ad_ip_instance axi_dmac axi_adrv9026_rx_dma
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.SYNC_TRANSFER_START 1
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32*$RX_NUM_OF_LANES]
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.MAX_BYTES_PER_BURST 256
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.FIFO_SIZE 32
# common cores
ad_ip_instance util_adxcvr util_adrv9026_xcvr
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_RATE 10
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_RATE 10
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_OUT_DIV 1
ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV 4
ad_ip_parameter util_adrv9026_xcvr CONFIG.CPLL_FBDIV_4_5 5
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CLK25_DIV 10
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_CLK25_DIV 10
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_PMA_CFG 0x001E7080
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020
ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_FBDIV 40
ad_ip_parameter util_adrv9026_xcvr CONFIG.QPLL_REFCLK_DIV 1
ad_ip_parameter util_adrv9026_xcvr CONFIG.TX_LANE_INVERT 6
ad_ip_parameter util_adrv9026_xcvr CONFIG.RX_LANE_INVERT 15
# xcvr interfaces
set tx_ref_clk tx_ref_clk_0
set rx_ref_clk rx_ref_clk_0
create_bd_port -dir I $tx_ref_clk
create_bd_port -dir I $rx_ref_clk
ad_connect $sys_cpu_resetn util_adrv9026_xcvr/up_rstn
ad_connect $sys_cpu_clk util_adrv9026_xcvr/up_clk
# Tx
ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_tx_xcvr axi_adrv9026_tx_jesd {2 3 1 0} core_clk
ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_0
ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_0
ad_xcvrpll $tx_ref_clk util_adrv9026_xcvr/qpll_ref_clk_4
ad_xcvrpll axi_adrv9026_tx_xcvr/up_pll_rst util_adrv9026_xcvr/up_qpll_rst_4
# Rx
ad_xcvrcon util_adrv9026_xcvr axi_adrv9026_rx_xcvr axi_adrv9026_rx_jesd {} core_clk
for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} {
set ch [expr $i]
ad_xcvrpll $rx_ref_clk util_adrv9026_xcvr/cpll_ref_clk_$ch
ad_xcvrpll axi_adrv9026_rx_xcvr/up_pll_rst util_adrv9026_xcvr/up_cpll_rst_$ch
}
# connections (dac)
ad_connect core_clk tx_adrv9026_tpl_core/link_clk
ad_connect axi_adrv9026_tx_jesd/tx_data tx_adrv9026_tpl_core/link
ad_connect core_clk util_adrv9026_tx_upack/clk
ad_connect core_clk_rstgen/peripheral_reset util_adrv9026_tx_upack/reset
for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
ad_connect tx_adrv9026_tpl_core/dac_enable_$i util_adrv9026_tx_upack/enable_$i
ad_connect util_adrv9026_tx_upack/fifo_rd_data_$i tx_adrv9026_tpl_core/dac_data_$i
}
ad_connect tx_adrv9026_tpl_core/dac_valid_0 util_adrv9026_tx_upack/fifo_rd_en
ad_connect core_clk axi_adrv9026_dacfifo/dac_clk
ad_connect core_clk_rstgen/peripheral_reset axi_adrv9026_dacfifo/dac_rst
ad_connect util_adrv9026_tx_upack/s_axis_valid VCC
ad_connect util_adrv9026_tx_upack/s_axis_ready axi_adrv9026_dacfifo/dac_valid
ad_connect util_adrv9026_tx_upack/s_axis_data axi_adrv9026_dacfifo/dac_data
ad_connect core_clk axi_adrv9026_dacfifo/dma_clk
ad_connect core_clk_rstgen/peripheral_reset axi_adrv9026_dacfifo/dma_rst
ad_connect core_clk axi_adrv9026_tx_dma/m_axis_aclk
ad_connect axi_adrv9026_dacfifo/dma_valid axi_adrv9026_tx_dma/m_axis_valid
ad_connect axi_adrv9026_dacfifo/dma_data axi_adrv9026_tx_dma/m_axis_data
ad_connect axi_adrv9026_dacfifo/dma_ready axi_adrv9026_tx_dma/m_axis_ready
ad_connect axi_adrv9026_dacfifo/dma_xfer_req axi_adrv9026_tx_dma/m_axis_xfer_req
ad_connect axi_adrv9026_dacfifo/dma_xfer_last axi_adrv9026_tx_dma/m_axis_last
ad_connect axi_adrv9026_dacfifo/dac_dunf tx_adrv9026_tpl_core/dac_dunf
ad_connect axi_adrv9026_dacfifo/bypass dac_fifo_bypass
ad_connect core_clk_rstgen/peripheral_aresetn axi_adrv9026_tx_dma/m_src_axi_aresetn
# connections (adc)
ad_connect core_clk rx_adrv9026_tpl_core/link_clk
ad_connect axi_adrv9026_rx_jesd/rx_sof rx_adrv9026_tpl_core/link_sof
ad_connect axi_adrv9026_rx_jesd/rx_data_tdata rx_adrv9026_tpl_core/link_data
ad_connect axi_adrv9026_rx_jesd/rx_data_tvalid rx_adrv9026_tpl_core/link_valid
ad_connect core_clk util_adrv9026_rx_cpack/clk
ad_connect core_clk_rstgen/peripheral_reset util_adrv9026_rx_cpack/reset
for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
ad_connect rx_adrv9026_tpl_core/adc_enable_$i util_adrv9026_rx_cpack/enable_$i
ad_connect rx_adrv9026_tpl_core/adc_data_$i util_adrv9026_rx_cpack/fifo_wr_data_$i
}
ad_connect $sys_dma_resetn axi_adrv9026_rx_dma/m_dest_axi_aresetn
ad_connect rx_adrv9026_tpl_core/adc_valid_0 util_adrv9026_rx_cpack/fifo_wr_en
ad_connect rx_adrv9026_tpl_core/adc_dovf util_adrv9026_rx_cpack/fifo_wr_overflow
ad_connect core_clk axi_adrv9026_rx_dma/fifo_wr_clk
ad_connect util_adrv9026_rx_cpack/packed_fifo_wr axi_adrv9026_rx_dma/fifo_wr
# interconnect (cpu)
ad_cpu_interconnect 0x44A00000 rx_adrv9026_tpl_core
ad_cpu_interconnect 0x44A04000 tx_adrv9026_tpl_core
ad_cpu_interconnect 0x44A80000 axi_adrv9026_tx_xcvr
ad_cpu_interconnect 0x44A90000 axi_adrv9026_tx_jesd
ad_cpu_interconnect 0x7c420000 axi_adrv9026_tx_dma
ad_cpu_interconnect 0x44A60000 axi_adrv9026_rx_xcvr
ad_cpu_interconnect 0x44AA0000 axi_adrv9026_rx_jesd
ad_cpu_interconnect 0x7c400000 axi_adrv9026_rx_dma
# gt uses hp0, and 100MHz clock for both DRP and AXI4
ad_mem_hp0_interconnect $sys_cpu_clk sys_ps8/S_AXI_HP0
ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9026_rx_xcvr/m_axi
# interconnect (mem/dac)
ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect $sys_dma_clk axi_adrv9026_rx_dma/m_dest_axi
ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect $sys_dma_clk axi_adrv9026_tx_dma/m_src_axi
# interrupts
ad_cpu_interrupt ps-10 mb-15 axi_adrv9026_tx_jesd/irq
ad_cpu_interrupt ps-11 mb-14 axi_adrv9026_rx_jesd/irq
ad_cpu_interrupt ps-13 mb-12 axi_adrv9026_tx_dma/irq
ad_cpu_interrupt ps-14 mb-11 axi_adrv9026_rx_dma/irq

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FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination
#adrv9026
D4 GBTCLK0_M2C_P FPGA_REF_CLK+ ref_clk_p #N/A #N/A
D5 GBTCLK0_M2C_N FPGA_REF_CLK- ref_clk_n #N/A #N/A
H4 CLK0_M2C_P FPGA_MMCM_CLK+ core_clk_p LVDS #N/A
H5 CLK0_M2C_N FPGA_MMCM_CLK- core_clk_n LVDS #N/A
A2 DP1_M2C_P SERDOUTA- rx_data_p[0] #N/A #N/A
A3 DP1_M2C_N SERDOUTA+ rx_data_n[0] #N/A #N/A
C6 DP0_M2C_P SERDOUTB- rx_data_p[1] #N/A #N/A
C7 DP0_M2C_N SERDOUTB+ rx_data_n[1] #N/A #N/A
A6 DP2_M2C_P SERDOUTC- rx_data_p[2] #N/A #N/A
A7 DP2_M2C_N SERDOUTC+ rx_data_n[2] #N/A #N/A
A10 DP3_M2C_P SERDOUTD- rx_data_p[3] #N/A #N/A
A11 DP3_M2C_N SERDOUTD+ rx_data_n[3] #N/A #N/A
A22 DP1_C2M_P SERDINC+ tx_data_p[0] #N/A #N/A
A23 DP1_C2M_N SERDINC- tx_data_n[0] #N/A #N/A
C2 DP0_C2M_P SERDIND- tx_data_p[1] #N/A #N/A
C3 DP0_C2M_N SERDIND+ tx_data_n[1] #N/A #N/A
A26 DP2_C2M_P SERDINB- tx_data_p[2] #N/A #N/A
A27 DP2_C2M_N SERDINB+ tx_data_n[2] #N/A #N/A
A30 DP3_C2M_P SERDINA+ tx_data_p[3] #N/A #N/A
A31 DP3_C2M_N SERDINA- tx_data_n[3] #N/A #N/A
G9 LA03_P SYNCIN1- rx_sync_p LVDS #N/A
G10 LA03_N SYNCIN1+ rx_sync_n LVDS #N/A
G36 LA33_P SYNCIN3- rx_sync_2_p LVDS #N/A
G37 LA33_N SYNCIN3+ rx_sync_2_n LVDS #N/A
G27 LA25_P SYNCIN2- rx_os_sync_p LVDS #N/A
G28 LA25_N SYNCIN2+ rx_os_sync_n LVDS #N/A
G6 LA00_CC_P FPGA_SYSREF+ sysref_p LVDS DIFF_TERM TRUE
G7 LA00_CC_N FPGA_SYSREF- sysref_n LVDS DIFF_TERM TRUE
H7 LA02_P SYNCOUT1+ tx_sync_p LVDS DIFF_TERM TRUE
H8 LA02_N SYNCOUT1- tx_sync_n LVDS DIFF_TERM TRUE
H28 LA24_P SYNCOUT2 tx_sync_1_p LVDS DIFF_TERM TRUE
H29 LA24_N SYNCOUT2 tx_sync_1_n LVDS DIFF_TERM TRUE
C26 LA27_P FMC_CLK_RESETB ad9528_reset_b LVCMOS18 #N/A
C27 LA27_N FMC_SYSREF_REQUEST ad9528_sysref_req LVCMOS18 #N/A
D11 LA05_P TEST adrv9026_test LVCMOS18 #N/A
C10 LA06_P ORX_CTRL_A adrv9026_orx_ctrl_a LVCMOS18 #N/A
C11 LA06_N ORX_CTRL_B adrv9026_orx_ctrl_b LVCMOS18 #N/A
D26 LA26_P ORX_CTRL_C adrv9026_orx_ctrl_c LVCMOS18 #N/A
C15 LA10_N ORX_CTRL_D adrv9026_orx_ctrl_d LVCMOS18 #N/A
D18 LA13_N RX1_ENABLE adrv9026_rx1_enable LVCMOS18 #N/A
C19 LA14_N RX2_ENABLE adrv9026_rx2_enable LVCMOS18 #N/A
D24 LA23_N RX3_ENABLE adrv9026_rx3_enable LVCMOS18 #N/A
D23 LA23_P RX4_ENABLE adrv9026_rx4_enable LVCMOS18 #N/A
D17 LA13_P TX1_ENABLE adrv9026_tx1_enable LVCMOS18 #N/A
C18 LA14_P TX2_ENABLE adrv9026_tx2_enable LVCMOS18 #N/A
D27 LA26_N TX3_ENABLE adrv9026_tx3_enable LVCMOS18 #N/A
C14 LA10_P TX4_ENABLE adrv9026_tx4_enable LVCMOS18 #N/A
H11 LA04_N GPINT1 adrv9026_gpint1 LVCMOS18 #N/A
H31 LA28_P GPINT2 adrv9026_gpint2 LVCMOS18 #N/A
H10 LA04_P RESETB adrv9026_reset_b LVCMOS18 #N/A
H19 LA15_P GPIO_0 adrv9026_gpio_00 LVCMOS18 #N/A
H20 LA15_N GPIO_1 adrv9026_gpio_01 LVCMOS18 #N/A
G18 LA16_P GPIO_2 adrv9026_gpio_02 LVCMOS18 #N/A
G19 LA16_N GPIO_3 adrv9026_gpio_03 LVCMOS18 #N/A
H25 LA21_P GPIO_4 adrv9026_gpio_04 LVCMOS18 #N/A
H26 LA21_N GPIO_5 adrv9026_gpio_05 LVCMOS18 #N/A
C22 LA18_CC_P GPIO_6 adrv9026_gpio_06 LVCMOS18 #N/A
C23 LA18_CC_N GPIO_7 adrv9026_gpio_07 LVCMOS18 #N/A
G25 LA22_N GPIO_8 adrv9026_gpio_08 LVCMOS18 #N/A
H22 LA19_P GPIO_9 adrv9026_gpio_09 LVCMOS18 #N/A
H23 LA19_N GPIO_10 adrv9026_gpio_10 LVCMOS18 #N/A
G21 LA20_P GPIO_11 adrv9026_gpio_11 LVCMOS18 #N/A
G22 LA20_N GPIO_12 adrv9026_gpio_12 LVCMOS18 #N/A
G31 LA29_N GPIO_13 adrv9026_gpio_13 LVCMOS18 #N/A
G30 LA29_P GPIO_14 adrv9026_gpio_14 LVCMOS18 #N/A
G24 LA22_P GPIO_15_FMC adrv9026_gpio_15 LVCMOS18 #N/A
G16 LA12_N GPIO_16 adrv9026_gpio_16 LVCMOS18 #N/A
G15 LA12_P GPIO_17 adrv9026_gpio_17 LVCMOS18 #N/A
D12 LA05_N GPIO_18 adrv9026_gpio_18 LVCMOS18 #N/A
D14 LA09_P SPI_CS0 spi_csn_adrv9026 LVCMOS18 #N/A
D15 LA09_N SPI_CS1 spi_csn_ad9528 LVCMOS18 #N/A
H13 LA07_P SPI_CLK spi_clk LVCMOS18 #N/A
G12 LA08_P SPI_DOUT spi_miso LVCMOS18 #N/A
H14 LA07_N SPI_DIN spi_mosi LVCMOS18 #N/A

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###############################################################################
## Copyright (C) 2018-2024 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
###############################################################################
PROJECT_NAME := adrv9026_zcu102
M_DEPS += ../common/adrv9026_bd.tcl
M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
LIB_DEPS += axi_dmac
LIB_DEPS += axi_sysid
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/axi_jesd204_tx
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += jesd204/jesd204_tx
LIB_DEPS += sysid_rom
LIB_DEPS += util_dacfifo
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr
include ../../scripts/project-xilinx.mk

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###############################################################################
## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
## FIFO depth is 18Mb - 1M samples
set dac_fifo_address_width 17
## NOTE: With this configuration the #36Kb BRAM utilization is at ~57%
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
set sys_cstring "sys rom custom string placeholder"
sysid_gen_sys_init_file $sys_cstring;
source ../common/adrv9026_bd.tcl

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###############################################################################
## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
#adrv9026
set_property -dict {PACKAGE_PIN G27} [get_ports ref_clk_p] ; ## D4 FMC1_GBTCLK0_M2C_C_P MGTREFCLK0P_130
set_property -dict {PACKAGE_PIN G28} [get_ports ref_clk_n] ; ## D5 FMC1_GBTCLK0_M2C_C_N MGTREFCLK0N_130
set_property -dict {PACKAGE_PIN AE7 IOSTANDARD LVDS} [get_ports core_clk_p] ; ## H4 FMC1_CLK0_M2C_P IO_L12P_T1U_N10_GC_65
set_property -dict {PACKAGE_PIN AF7 IOSTANDARD LVDS} [get_ports core_clk_n] ; ## H5 FMC1_CLK0_M2C_N IO_L12N_T1U_N11_GC_65
set_property -dict {PACKAGE_PIN D33} [get_ports rx_data_p[0]] ; ## A2 FMC1_DP1_M2C_P MGTHRXP1_130
set_property -dict {PACKAGE_PIN D34} [get_ports rx_data_n[0]] ; ## A3 FMC1_DP1_M2C_N MGTHRXN1_130
set_property -dict {PACKAGE_PIN E31} [get_ports rx_data_p[1]] ; ## C6 FMC1_DP0_M2C_P MGTHRXP0_130
set_property -dict {PACKAGE_PIN E32} [get_ports rx_data_n[1]] ; ## C7 FMC1_DP0_M2C_N MGTHRXN0_130
set_property -dict {PACKAGE_PIN C31} [get_ports rx_data_p[2]] ; ## A6 FMC1_DP2_M2C_P MGTHRXP2_130
set_property -dict {PACKAGE_PIN C32} [get_ports rx_data_n[2]] ; ## A7 FMC1_DP2_M2C_N MGTHRXN2_130
set_property -dict {PACKAGE_PIN B33} [get_ports rx_data_p[3]] ; ## A10 FMC1_DP3_M2C_P MGTHRXP3_130
set_property -dict {PACKAGE_PIN B34} [get_ports rx_data_n[3]] ; ## A11 FMC1_DP3_M2C_N MGTHRXN3_130
set_property -dict {PACKAGE_PIN D29} [get_ports tx_data_p[0]] ; ## A22 FMC1_DP1_C2M_P MGTHTXP1_130 (tx_data_p[2])
set_property -dict {PACKAGE_PIN D30} [get_ports tx_data_n[0]] ; ## A23 FMC1_DP1_C2M_N MGTHTXN1_130 (tx_data_n[2])
set_property -dict {PACKAGE_PIN F29} [get_ports tx_data_p[1]] ; ## C2 FMC1_DP0_C2M_P MGTHTXP0_130 (tx_data_p[3])
set_property -dict {PACKAGE_PIN F30} [get_ports tx_data_n[1]] ; ## C3 FMC1_DP0_C2M_N MGTHTXN0_130 (tx_data_n[3])
set_property -dict {PACKAGE_PIN B29} [get_ports tx_data_p[2]] ; ## A26 FMC1_DP2_C2M_P MGTHTXP2_130 (tx_data_p[1])
set_property -dict {PACKAGE_PIN B30} [get_ports tx_data_n[2]] ; ## A27 FMC1_DP2_C2M_N MGTHTXN2_130 (tx_data_n[1])
set_property -dict {PACKAGE_PIN A31} [get_ports tx_data_p[3]] ; ## A30 FMC1_DP3_C2M_P MGTHTXP3_130 (tx_data_p[0])
set_property -dict {PACKAGE_PIN A32} [get_ports tx_data_n[3]] ; ## A31 FMC1_DP3_C2M_N MGTHTXN3_130 (tx_data_n[0])
set_property -dict {PACKAGE_PIN AH1 IOSTANDARD LVDS} [get_ports rx_sync_p] ; ## G9 FMC1_LA03_P IO_L22P_T3U_N6_DBC_AD0P_65
set_property -dict {PACKAGE_PIN AJ1 IOSTANDARD LVDS} [get_ports rx_sync_n] ; ## G10 FMC1_LA03_N IO_L22N_T3U_N7_DBC_AD0N_65
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVDS} [get_ports rx_os_sync_p] ; ## G27 FMC1_LA25_P IO_L1P_T0L_N0_DBC_65
set_property -dict {PACKAGE_PIN AF10 IOSTANDARD LVDS} [get_ports rx_os_sync_n] ; ## G28 FMC1_LA25_N IO_L1N_T0L_N1_DBC_65
set_property -dict {PACKAGE_PIN AE5 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports sysref_p] ; ## G6 FMC1_LA00_CC_P IO_L13P_T2L_N0_GC_QBC_65
set_property -dict {PACKAGE_PIN AF5 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports sysref_n] ; ## G7 FMC1_LA00_CC_N IO_L13N_T2L_N1_GC_QBC_65
set_property -dict {PACKAGE_PIN AD2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H7 FMC1_LA02_P IO_L23P_T3U_N8_I2C_SCLK_65
set_property -dict {PACKAGE_PIN AD1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H8 FMC1_LA02_N IO_L23N_T3U_N9_65
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_1_p] ; ## H28 FMC1_LA24_P IO_L2P_T0L_N2_65
set_property -dict {PACKAGE_PIN AH11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports tx_sync_1_n] ; ## H29 FMC1_LA24_N IO_L2N_T0L_N3_65
set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS18} [get_ports ad9528_reset_b] ; ## C26 FMC1_LA27_P IO_L3P_T0L_N4_AD15P_67
set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS18} [get_ports ad9528_sysref_req] ; ## C27 FMC1_LA27_N IO_L3N_T0L_N5_AD15N_67
set_property -dict {PACKAGE_PIN AG3 IOSTANDARD LVCMOS18} [get_ports adrv9026_test] ; ## D11 FMC1_LA05_P IO_L20P_T3L_N2_AD1P_65
set_property -dict {PACKAGE_PIN AH2 IOSTANDARD LVCMOS18} [get_ports adrv9026_orx_ctrl_a] ; ## C10 FMC1_LA06_P IO_L19P_T3L_N0_DBC_AD9P_65
set_property -dict {PACKAGE_PIN AJ2 IOSTANDARD LVCMOS18} [get_ports adrv9026_orx_ctrl_b] ; ## C11 FMC1_LA06_N IO_L19N_T3L_N1_DBC_AD9N_65
set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS18} [get_ports adrv9026_orx_ctrl_c] ; ## D26 FMC1_LA26_P IO_L4P_T0U_N6_DBC_AD7P_67
set_property -dict {PACKAGE_PIN AJ4 IOSTANDARD LVCMOS18} [get_ports adrv9026_orx_ctrl_d] ; ## C15 FMC1_LA10_N IO_L15N_T2L_N5_AD11N_65
set_property -dict {PACKAGE_PIN AH8 IOSTANDARD LVCMOS18} [get_ports adrv9026_rx1_enable] ; ## D18 FMC1_LA13_N IO_L8N_T1L_N3_AD5N_65
set_property -dict {PACKAGE_PIN AH6 IOSTANDARD LVCMOS18} [get_ports adrv9026_rx2_enable] ; ## C19 FMC1_LA14_N IO_L7N_T1L_N1_QBC_AD13N_65
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS18} [get_ports adrv9026_rx3_enable] ; ## D24 FMC1_LA23_N IO_L3N_T0L_N5_AD15N_65
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS18} [get_ports adrv9026_rx4_enable] ; ## D23 FMC1_LA23_P IO_L3P_T0L_N4_AD15P_65
set_property -dict {PACKAGE_PIN AG8 IOSTANDARD LVCMOS18} [get_ports adrv9026_tx1_enable] ; ## D17 FMC1_LA13_P IO_L8P_T1L_N2_AD5P_65
set_property -dict {PACKAGE_PIN AH7 IOSTANDARD LVCMOS18} [get_ports adrv9026_tx2_enable] ; ## C18 FMC1_LA14_P IO_L7P_T1L_N0_QBC_AD13P_65
set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS18} [get_ports adrv9026_tx3_enable] ; ## D27 FMC1_LA26_N IO_L4N_T0U_N7_DBC_AD7N_67
set_property -dict {PACKAGE_PIN AH4 IOSTANDARD LVCMOS18} [get_ports adrv9026_tx4_enable] ; ## C14 FMC1_LA10_P IO_L15P_T2L_N4_AD11P_65
set_property -dict {PACKAGE_PIN AF1 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpint1] ; ## H11 FMC1_LA04_N IO_L21N_T3L_N5_AD8N_65
set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpint2] ; ## H31 FMC1_LA28_P IO_L2P_T0L_N2_67
set_property -dict {PACKAGE_PIN AF2 IOSTANDARD LVCMOS18} [get_ports adrv9026_reset_b] ; ## H10 FMC1_LA04_P IO_L21P_T3L_N4_AD8P_65
set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_00] ; ## H19 FMC1_LA15_P IO_L6P_T0U_N10_AD6P_65
set_property -dict {PACKAGE_PIN AE9 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_01] ; ## H20 FMC1_LA15_N IO_L6N_T0U_N11_AD6N_65
set_property -dict {PACKAGE_PIN AG10 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_02] ; ## G18 FMC1_LA16_P IO_L5P_T0U_N8_AD14P_65
set_property -dict {PACKAGE_PIN AG9 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_03] ; ## G19 FMC1_LA16_N IO_L5N_T0U_N9_AD14N_65
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_04] ; ## H25 FMC1_LA21_P IO_L1P_T0L_N0_DBC_66
set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_05] ; ## H26 FMC1_LA21_N IO_L1N_T0L_N1_DBC_66
set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_06] ; ## C22 FMC1_LA18_CC_P IO_L11N_T1U_N9_GC_66
set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_07] ; ## C23 FMC1_LA18_CC_N IO_L11N_T1U_N9_GC_66
set_property -dict {PACKAGE_PIN AG11 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_08] ; ## G25 FMC1_LA22_N IO_L4N_T0U_N7_DBC_AD7N_65
set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_09] ; ## H22 FMC1_LA19_P IO_L3P_T0L_N4_AD15P_66
set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_10] ; ## H23 FMC1_LA19_N IO_L3N_T0L_N5_AD15N_66
set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_11] ; ## G21 FMC1_LA20_P IO_L2P_T0L_N2_66
set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_12] ; ## G22 FMC1_LA20_N IO_L2N_T0L_N3_66
set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_13] ; ## G31 FMC1_LA29_N IO_L1N_T0L_N1_DBC_67
set_property -dict {PACKAGE_PIN W12 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_14] ; ## G30 FMC1_LA29_P IO_L1P_T0L_N0_DBC_67
set_property -dict {PACKAGE_PIN AF11 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_15] ; ## G24 FMC1_LA22_P IO_L4P_T0U_N6_DBC_AD7P_SMBALERT_65
set_property -dict {PACKAGE_PIN AD6 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_16] ; ## G16 FMC1_LA12_N IO_L9N_T1L_N5_AD12N_65
set_property -dict {PACKAGE_PIN AD7 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_17] ; ## G15 FMC1_LA12_P IO_L9P_T1L_N4_AD12P_65
set_property -dict {PACKAGE_PIN AH3 IOSTANDARD LVCMOS18} [get_ports adrv9026_gpio_18] ; ## D12 FMC1_LA05_N IO_L20N_T3L_N3_AD1N_65
set_property -dict {PACKAGE_PIN AE2 IOSTANDARD LVCMOS18} [get_ports spi_csn_adrv9026] ; ## D14 FMC1_LA09_P IO_L24P_T3U_N10_PERSTN1_I2C_SDA_65
set_property -dict {PACKAGE_PIN AE1 IOSTANDARD LVCMOS18} [get_ports spi_csn_ad9528] ; ## D15 FMC1_LA09_N IO_L24N_T3U_N11_PERSTN0_65
set_property -dict {PACKAGE_PIN AD4 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## H13 FMC1_LA07_P IO_L18P_T2U_N10_AD2P_65
set_property -dict {PACKAGE_PIN AE3 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## G12 FMC1_LA08_P IO_L17P_T2U_N8_AD10P_65
set_property -dict {PACKAGE_PIN AE4 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## H14 FMC1_LA07_N IO_L18N_T2U_N11_AD2N_65
# clocks
create_clock -name ref_clk -period 4.00 [get_ports ref_clk_p]
create_clock -name core_clk -period 4.00 [get_ports core_clk_p]

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###############################################################################
## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project adrv9026_zcu102 0 [list \
TX_JESD_M [get_env_param TX_JESD_M 8 ] \
TX_JESD_L [get_env_param TX_JESD_L 4 ] \
TX_JESD_S [get_env_param TX_JESD_S 1 ] \
RX_JESD_M [get_env_param RX_JESD_M 8 ] \
RX_JESD_L [get_env_param RX_JESD_L 4 ] \
RX_JESD_S [get_env_param RX_JESD_S 1 ] \
]
adi_project_files adrv9026_zcu102 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
adi_project_run adrv9026_zcu102

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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
input [12:0] gpio_bd_i,
output [ 7:0] gpio_bd_o,
inout iic_scl,
inout iic_sda,
input ref_clk_p,
input ref_clk_n,
input core_clk_p,
input core_clk_n,
input [ 3:0] rx_data_p,
input [ 3:0] rx_data_n,
output [ 3:0] tx_data_p,
output [ 3:0] tx_data_n,
output rx_sync_p,
output rx_sync_n,
output rx_os_sync_p,
output rx_os_sync_n,
input tx_sync_p,
input tx_sync_n,
input tx_sync_1_p,
input tx_sync_1_n,
input sysref_p,
input sysref_n,
output spi_csn_ad9528,
output spi_csn_adrv9026,
output spi_clk,
output spi_mosi,
input spi_miso,
inout ad9528_reset_b,
inout ad9528_sysref_req,
inout adrv9026_tx1_enable,
inout adrv9026_tx2_enable,
inout adrv9026_tx3_enable,
inout adrv9026_tx4_enable,
inout adrv9026_rx1_enable,
inout adrv9026_rx2_enable,
inout adrv9026_rx3_enable,
inout adrv9026_rx4_enable,
inout adrv9026_test,
inout adrv9026_reset_b,
inout adrv9026_gpint1,
inout adrv9026_gpint2,
inout adrv9026_orx_ctrl_a,
inout adrv9026_orx_ctrl_b,
inout adrv9026_orx_ctrl_c,
inout adrv9026_orx_ctrl_d,
inout adrv9026_gpio_00,
inout adrv9026_gpio_01,
inout adrv9026_gpio_02,
inout adrv9026_gpio_03,
inout adrv9026_gpio_04,
inout adrv9026_gpio_05,
inout adrv9026_gpio_06,
inout adrv9026_gpio_07,
inout adrv9026_gpio_08,
inout adrv9026_gpio_09,
inout adrv9026_gpio_10,
inout adrv9026_gpio_11,
inout adrv9026_gpio_12,
inout adrv9026_gpio_13,
inout adrv9026_gpio_14,
inout adrv9026_gpio_15,
inout adrv9026_gpio_16,
inout adrv9026_gpio_17,
inout adrv9026_gpio_18
);
// internal signals
wire [94:0] gpio_i;
wire [94:0] gpio_o;
wire [94:0] gpio_t;
wire [20:0] gpio_bd;
wire [ 2:0] spi_csn;
wire ref_clk;
wire rx_sync;
wire rx_os_sync;
wire tx_sync;
wire tx_sync_1;
wire sysref;
assign gpio_i[94:69] = gpio_o[94:69];
assign gpio_i[31:21] = gpio_o[31:21];
assign rx_os_sync = 1'b0;
// instantiations
IBUFDS_GTE4 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (ref_clk_p),
.IB (ref_clk_n),
.O (ref_clk),
.ODIV2 ());
IBUFDS i_core_clk_ibufds_1 (
.I (core_clk_p),
.IB (core_clk_n),
.O (core_clk_in));
BUFG i_core_clk_bufg (
.I (core_clk_in),
.O (core_clk));
OBUFDS i_obufds_rx_sync (
.I (~rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
OBUFDS i_obufds_rx_os_sync (
.I (rx_os_sync),
.O (rx_os_sync_p),
.OB (rx_os_sync_n));
IBUFDS i_ibufds_tx_sync (
.I (tx_sync_p),
.IB (tx_sync_n),
.O (tx_sync));
IBUFDS i_ibufds_tx_sync_1 (
.I (tx_sync_1_p),
.IB (tx_sync_1_n),
.O (tx_sync_1));
IBUFDS i_ibufds_sysref (
.I (sysref_p),
.IB (sysref_n),
.O (sysref));
ad_iobuf #(
.DATA_WIDTH(37)
) i_iobuf (
.dio_t ({gpio_t[68:32]}),
.dio_i ({gpio_o[68:32]}),
.dio_o ({gpio_i[68:32]}),
.dio_p ({ ad9528_reset_b, // 68
ad9528_sysref_req, // 67
adrv9026_tx1_enable, // 66
adrv9026_tx2_enable, // 65
adrv9026_tx3_enable, // 64
adrv9026_tx4_enable, // 63
adrv9026_rx1_enable, // 62
adrv9026_rx2_enable, // 61
adrv9026_rx3_enable, // 60
adrv9026_rx4_enable, // 59
adrv9026_test, // 58
adrv9026_reset_b, // 57
adrv9026_gpint1, // 56
adrv9026_gpint2, // 55
adrv9026_orx_ctrl_a, // 54
adrv9026_orx_ctrl_b, // 53
adrv9026_orx_ctrl_c, // 52
adrv9026_orx_ctrl_d, // 51
adrv9026_gpio_00, // 50
adrv9026_gpio_01, // 49
adrv9026_gpio_02, // 48
adrv9026_gpio_03, // 47
adrv9026_gpio_04, // 46
adrv9026_gpio_05, // 45
adrv9026_gpio_06, // 44
adrv9026_gpio_07, // 43
adrv9026_gpio_08, // 42
adrv9026_gpio_09, // 41
adrv9026_gpio_10, // 40
adrv9026_gpio_11, // 39
adrv9026_gpio_12, // 38
adrv9026_gpio_13, // 37
adrv9026_gpio_14, // 36
adrv9026_gpio_15, // 35
adrv9026_gpio_16, // 34
adrv9026_gpio_17, // 33
adrv9026_gpio_18})); // 32
assign gpio_i[ 7: 0] = gpio_o[ 7: 0];
assign gpio_i[20: 8] = gpio_bd_i;
assign gpio_bd_o = gpio_o[ 7: 0];
assign spi_csn_adrv9026 = spi_csn[0];
assign spi_csn_ad9528 = spi_csn[1];
system_wrapper i_system_wrapper (
.dac_fifo_bypass (gpio_o[69]),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.core_clk (core_clk),
.rx_data_0_n (rx_data_n[0]),
.rx_data_0_p (rx_data_p[0]),
.rx_data_1_n (rx_data_n[1]),
.rx_data_1_p (rx_data_p[1]),
.rx_data_2_n (rx_data_n[2]),
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_ref_clk_0 (ref_clk),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (sysref),
.spi0_sclk (spi_clk),
.spi0_csn (spi_csn),
.spi0_miso (spi_miso),
.spi0_mosi (spi_mosi),
.spi1_sclk (),
.spi1_csn (),
.spi1_miso (1'b0),
.spi1_mosi (),
.tx_data_0_n (tx_data_n[0]),
.tx_data_0_p (tx_data_p[0]),
.tx_data_1_n (tx_data_n[1]),
.tx_data_1_p (tx_data_p[1]),
.tx_data_2_n (tx_data_n[2]),
.tx_data_2_p (tx_data_p[2]),
.tx_data_3_n (tx_data_n[3]),
.tx_data_3_p (tx_data_p[3]),
.tx_ref_clk_0 (ref_clk),
.tx_sync_0 (tx_sync),
.tx_sysref_0 (sysref));
endmodule