ad_csc(RGB2CrYCb): use signed multiplication.
parent
265781f29a
commit
74eacc2369
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@ -38,8 +38,7 @@
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module ad_csc #(
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parameter DELAY_DW = 16,
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parameter COLOR_N = 1) (
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parameter DELAY_DW = 16) (
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// data
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@ -52,76 +51,69 @@ module ad_csc #(
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input signed [16:0] C1,
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input signed [16:0] C2,
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input signed [16:0] C3,
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input signed [24:0] C4,
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input signed [23:0] C4,
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// sync is delay matched
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output reg [DELAY_DW-1:0] csc_sync,
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output [ 7:0] csc_data);
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output [ DELAY_DW-1:0] csc_sync,
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output [ 7:0] csc_data);
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localparam Y = 1;
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localparam Cb = 2;
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localparam Cr = 3;
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localparam PIXEL_WD = 9; // sign extended
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localparam MUL_DW = MUL_COEF_DW + PIXEL_WD -1;
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// internal wires
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reg [ 23:0] data_d1;
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reg [ 23:0] data_d2;
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reg [ 33:0] data_1;
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reg [ 33:0] data_2;
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reg [ 33:0] data_3;
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reg [DELAY_DW:0] sync_1_m;
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reg [DELAY_DW:0] sync_2_m;
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reg [DELAY_DW:0] sync_3_m;
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reg [ 33:0] s_data_1;
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reg [ 33:0] s_data_2;
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reg [ 33:0] s_data_3;
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reg signed [ 23:0] data_d1;
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reg signed [ 23:0] data_d2;
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reg signed [ MUL_DW:0] data_1;
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reg signed [ MUL_DW:0] data_2;
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reg signed [ MUL_DW:0] data_3;
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reg signed [ MUL_DW:0] s_data_1;
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reg signed [ MUL_DW:0] s_data_2;
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reg signed [ MUL_DW:0] s_data_3;
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reg [DELAY_DW-1:0] sync_1_m;
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reg [DELAY_DW-1:0] sync_2_m;
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reg [DELAY_DW-1:0] sync_3_m;
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reg [DELAY_DW-1:0] sync_4_m;
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reg [ 7:0] csc_data_d;
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wire signed [33:0] data_1_s;
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wire signed [33:0] data_2_s;
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wire signed [33:0] data_3_s;
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wire signed [8:0] color1;
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wire signed [8:0] color2;
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wire signed [8:0] color3;
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// Let the tools decide what logic to infer
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// delay signals
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always @(posedge clk) begin
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data_d1 <= data;
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data_d2 <= data_d1;
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data_1 <= {9'd0, data[23:16]} * C1; // R
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data_2 <= {9'd0, data_d1[15: 8]} * C2; // G
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data_3 <= {9'd0, data_d2[ 7: 0]} * C3; // B
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sync_1_m <= sync;
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end
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generate
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if (COLOR_N == Y) begin
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assign data_1_s = data_1;
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assign data_2_s = data_2;
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assign data_3_s = data_3;
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end
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if (COLOR_N == Cb) begin
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assign data_1_s = ~data_1;
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assign data_2_s = ~data_2;
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assign data_3_s = data_3;
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end
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if (COLOR_N == Cr) begin
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assign data_1_s = data_1;
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assign data_2_s = ~data_2;
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assign data_3_s = ~data_3;
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end
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endgenerate
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always @(posedge clk) begin
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s_data_1 <= data_1_s + C4;
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s_data_2 <= s_data_1 + data_2_s;
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s_data_3 <= s_data_2 + data_3_s;
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sync_2_m <= sync_1_m;
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sync_3_m <= sync_2_m;
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csc_sync <= sync_3_m;
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sync_4_m <= sync_3_m;
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csc_sync <= sync_4_m;
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end
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assign csc_data = s_data_3[23:16];
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assign color1 = {1'd0, data[23:16]};
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assign color2 = {1'd0, data_d1[15: 8]};
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assign color3 = {1'd0, data_d2[ 7: 0]};
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// pipeline DSPs for multiplications and additions
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always @(posedge clk) begin
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data_1 <= color1 * C1;
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data_2 <= color2 * C2;
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data_3 <= color3 * C3;
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end
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always @(posedge clk) begin
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s_data_1 <= data_1 + C4;
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s_data_2 <= s_data_1 + data_2;
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s_data_3 <= s_data_2 + data_3;
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end
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assign csc_data = s_data_3[23:16];
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endmodule
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@ -61,48 +61,45 @@ module ad_csc_RGB2CrYCb #(
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// Cr (red-diff)
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ad_csc #(
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.DELAY_DW(DELAY_DATA_WIDTH),
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.COLOR_N(3))
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.DELAY_DW(DELAY_DATA_WIDTH))
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j_csc_1_Cr (
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.clk (clk),
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.sync (RGB_sync),
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.data (RGB_data),
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.C1 (17'h7070),
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.C2 (17'h5e27),
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.C3 (17'h1248),
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.C4 (24'h800002),
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.C1 ( 17'd28784), // 112.439
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.C2 (-17'd24103), // -94.154
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.C3 (-17'd4681), // -18.285
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.C4 ( 24'd8388608), // 128
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.csc_sync (CrYCb_sync),
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.csc_data (CrYCb_data[23:16]));
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// Y (luma)
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ad_csc #(
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.DELAY_DW(0),
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.COLOR_N(1))
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.DELAY_DW(0))
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j_csc_1_Y (
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.clk (clk),
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.sync (1'd0),
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.data (RGB_data),
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.C1 (17'h041bd),
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.C2 (17'h0810e),
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.C3 (17'h01910),
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.C4 (24'h100000),
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.C1 (17'd16829), // 65.739
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.C2 (17'd33039), // 129.057
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.C3 (17'd6416), // 25.064
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.C4 (24'd1048576), // 16
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.csc_sync (),
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.csc_data (CrYCb_data[15:8]));
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// Cb (blue-diff)
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ad_csc #(
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.DELAY_DW(0),
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.COLOR_N(2))
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.DELAY_DW(0))
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j_csc_1_Cb (
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.clk (clk),
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.sync (1'd0),
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.data (RGB_data),
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.C1 (17'h25f1),
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.C2 (17'h4a7e),
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.C3 (17'h7070),
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.C4 (24'h800002),
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.C1 (-17'd9714), // -37.945
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.C2 (-17'd19070), // -74.494
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.C3 ( 17'd28784), // 112.439
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.C4 (24'd8388608), // 128
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.csc_sync (),
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.csc_data (CrYCb_data[7:0]));
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