ad_rst: ultrascale -dual stage

main
Rejeesh Kutty 2014-11-05 16:47:41 -05:00
parent 0425202da5
commit 74ec396b27
1 changed files with 14 additions and 6 deletions

View File

@ -53,14 +53,22 @@ module ad_rst (
input clk;
output rst;
// internal registers
reg rst_p = 'd0;
reg rst = 'd0;
// simple reset gen
FDPE #(.INIT(1'b1)) i_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (preset),
.C (clk),
.Q (rst));
always @(posedge clk or posedge preset) begin
if (preset == 1'b1) begin
rst_p <= 1'd1;
rst <= 1'd1;
end else begin
rst_p <= 1'b0;
rst <= rst_p;
end
end
endmodule