From 74f9a99655d42f6d07836075dffa66b23a614995 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Fri, 9 Jun 2017 16:20:49 -0400 Subject: [PATCH] fmcjesdadc1/a5gt- altera 16.1 updates --- projects/fmcjesdadc1/a5gt/system_constr.sdc | 21 ++++---------------- projects/fmcjesdadc1/a5gt/system_project.tcl | 15 ++++++-------- 2 files changed, 10 insertions(+), 26 deletions(-) diff --git a/projects/fmcjesdadc1/a5gt/system_constr.sdc b/projects/fmcjesdadc1/a5gt/system_constr.sdc index d9369ae46..9b6a80304 100644 --- a/projects/fmcjesdadc1/a5gt/system_constr.sdc +++ b/projects/fmcjesdadc1/a5gt/system_constr.sdc @@ -11,24 +11,11 @@ set_clock_groups -exclusive \ -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \ -group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] -set_false_path -to [get_registers *sysref_en_m1*] - -set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -through [get_nets *altera_jesd204_rx_ctl_inst*] \ - -to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] - -set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \ - -through [get_nets *altera_jesd204_rx_ctl_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] - -set_false_path -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -through [get_nets *altera_jesd204_rx_csr_inst*] \ - -to [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] - -set_false_path -from [get_clocks {i_system_bd|avl_ad9250_xcvr|alt_core_pll|altera_pll_i|arriav_pll|counter[0].output_counter|divclk}] \ - -through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] +set_false_path -from [get_clocks *divclk*] -through [get_nets *altera_jesd204*] -to [get_clocks *pll_avl_clk*] +set_false_path -from [get_clocks *pll_avl_clk*] -through [get_nets *altera_jesd204*] -to [get_clocks *divclk*] if {[string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)]} { - set_max_delay -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll8~PLL_OUTPUT_COUNTER|divclk}] \ - -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll4~PLL_OUTPUT_COUNTER|divclk}] 0.150 - set_min_delay -from [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll8~PLL_OUTPUT_COUNTER|divclk}] \ - -to [get_clocks {i_system_bd|sys_ddr3_cntrl|pll0|pll4~PLL_OUTPUT_COUNTER|divclk}] 0.000 + set_max_delay -from [get_clocks *pll_hr_clk*] -to [get_clocks *pll_afi_phy_clk*] 0.150 + set_min_delay -from [get_clocks *pll_hr_clk*] -to [get_clocks *pll_afi_phy_clk*] 0.000 } diff --git a/projects/fmcjesdadc1/a5gt/system_project.tcl b/projects/fmcjesdadc1/a5gt/system_project.tcl index 832085388..9a0cf42d1 100755 --- a/projects/fmcjesdadc1/a5gt/system_project.tcl +++ b/projects/fmcjesdadc1/a5gt/system_project.tcl @@ -1,18 +1,15 @@ -load_package flow - source ../../scripts/adi_env.tcl -project_new fmcjesdadc1_a5gt -overwrite +source ../../scripts/adi_project_alt.tcl -source "../../common/a5gt/a5gt_system_assign.tcl" +adi_project_altera fmcjesdadc1_a5gt + +source $ad_hdl_dir/projects/common/a5gt/a5gt_system_assign.tcl + +# files set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v set_global_assignment -name VERILOG_FILE ../../../library/common/ad_sysref_gen.v -set_global_assignment -name VERILOG_FILE system_top.v -set_global_assignment -name QSYS_FILE system_bd.qsys - -set_global_assignment -name SDC_FILE system_constr.sdc -set_global_assignment -name TOP_LEVEL_ENTITY system_top # reference clock