common/up_* : Make up_rstn synchronous to up_clk

The up_rstn is driven by s_axi_resetn, which is generated by a
Processor System Reset module. (connected to port peripheral_aresetn)
Therefor using this reset signal as an asynchronous reset is redundant,
and a bad design practice at the same time. Asynchronous reset should be
used if it's inevitable.

library/common/up_adc_channel.v

@@ -179,7 +179,7 @@ module up_adc_channel #(
 
   assign up_wack = up_wack_int;
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_wack_int <= 'd0;
       up_adc_lb_enb <= 'd0;
@@ -199,7 +199,7 @@ module up_adc_channel #(
     up_adc_iqcor_enb <= 'd0;
   end
   end else begin
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_adc_iqcor_enb <= 'd0;
     end else begin
@@ -217,7 +217,7 @@ module up_adc_channel #(
     up_adc_dcfilt_enb <= 'd0;
   end
   end else begin
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_adc_dcfilt_enb <= 'd0;
     end else begin
@@ -237,7 +237,7 @@ module up_adc_channel #(
     up_adc_dfmt_enable <= 'd0;
   end
   end else begin
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_adc_dfmt_se <= 'd0;
       up_adc_dfmt_type <= 'd0;
@@ -253,7 +253,7 @@ module up_adc_channel #(
   end
   endgenerate
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_adc_pn_type <= 'd0;
       up_adc_enable <= 'd0;
@@ -290,7 +290,7 @@ module up_adc_channel #(
     up_adc_dcfilt_coeff <= 'd0;
   end
   end else begin
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_adc_dcfilt_offset <= 'd0;
       up_adc_dcfilt_coeff <= 'd0;
@@ -311,7 +311,7 @@ module up_adc_channel #(
     up_adc_iqcor_coeff_2 <= 'd0;
   end
   end else begin
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_adc_iqcor_coeff_1 <= 'd0;
       up_adc_iqcor_coeff_2 <= 'd0;
@@ -325,7 +325,7 @@ module up_adc_channel #(
   end
   endgenerate
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_adc_pnseq_sel <= 'd0;
       up_adc_data_sel <= 'd0;
@@ -349,7 +349,7 @@ module up_adc_channel #(
     up_usr_decimation_n_int <= 'd0;
   end
   end else begin
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_usr_datatype_be_int <= 'd0;
       up_usr_datatype_signed_int <= 'd0;
@@ -380,7 +380,7 @@ module up_adc_channel #(
   assign up_rack = up_rack_int;
   assign up_rdata = up_rdata_int;
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_rack_int <= 'd0;
       up_rdata_int <= 'd0;
@@ -410,7 +410,7 @@ module up_adc_channel #(
 
   // change coefficients to 2's complements
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_adc_iqcor_coeff_tc_1 <= 16'd0;
       up_adc_iqcor_coeff_tc_2 <= 16'd0;
@@ -422,7 +422,7 @@ module up_adc_channel #(
 
   // data/pn sources
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_adc_pnseq_sel_m <= 4'd0;
       up_adc_data_sel_m <= 4'd0;

library/common/up_adc_common.v

@@ -163,7 +163,7 @@ module up_adc_common #(
   assign up_wack = up_wack_int;
   assign up_adc_ce = up_adc_clk_enb_int;
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_adc_clk_enb_int <= 1'd1;
       up_core_preset <= 1'd1;
@@ -228,7 +228,7 @@ module up_adc_common #(
     up_drp_rdata_hold <= 'd0;
   end
   end else begin
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_drp_sel_int <= 'd0;
       up_drp_wr_int <= 'd0;
@@ -265,7 +265,7 @@ module up_adc_common #(
   end
   endgenerate
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_status_ovf <= 'd0;
       up_status_unf <= 'd0;
@@ -291,7 +291,7 @@ module up_adc_common #(
     up_usr_chanmax_int <= 'd0;
   end
   end else begin
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_usr_chanmax_int <= 'd0;
     end else begin
@@ -311,7 +311,7 @@ module up_adc_common #(
     up_adc_gpio_out_int <= 'd0;
   end
   end else begin
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_adc_gpio_out_int <= 'd0;
     end else begin
@@ -329,7 +329,7 @@ module up_adc_common #(
     up_adc_start_code <= 'd0;
   end
   end else begin
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_adc_start_code <= 'd0;
     end else begin
@@ -343,7 +343,7 @@ module up_adc_common #(
 
   // timer with premature termination
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_timer <= 32'd0;
     end else begin
@@ -360,7 +360,7 @@ module up_adc_common #(
   assign up_rack = up_rack_int;
   assign up_rdata = up_rdata_int;
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_rack_int <= 'd0;
       up_rdata_int <= 'd0;

library/common/up_axi.v

@@ -110,7 +110,7 @@ module up_axi #(
   assign up_axi_bvalid = up_axi_bvalid_int;
   assign up_axi_bresp = 2'd0;
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 1'b0) begin
       up_axi_awready_int <= 'd0;
       up_axi_wready_int <= 'd0;
@@ -139,7 +139,7 @@ module up_axi #(
   assign up_wdata = up_wdata_int;
   assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack);
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 1'b0) begin
       up_wack_d <= 'd0;
       up_wsel <= 'd0;
@@ -179,7 +179,7 @@ module up_axi #(
   assign up_axi_rdata = up_axi_rdata_int;
   assign up_axi_rresp = 2'd0;
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 1'b0) begin
       up_axi_arready_int <= 'd0;
       up_axi_rvalid_int <= 'd0;
@@ -205,7 +205,7 @@ module up_axi #(
   assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack);
   assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata;
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 1'b0) begin
       up_rack_d <= 'd0;
       up_rdata_d <= 'd0;

library/common/up_clock_mon.v

@@ -72,7 +72,7 @@ module up_clock_mon #(
   // Capture on the falling edge of running
   assign up_count_capture_s = up_count_running_m3 == 1'b1 && up_count_running_m2 == 1'b0;
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_count_running_m1 <= 1'b0;
       up_count_running_m2 <= 1'b0;
@@ -84,7 +84,7 @@ module up_clock_mon #(
     end
   end
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_d_count <= 'd0;
       up_count_run <= 1'b0;

library/common/up_delay_cntrl.v

@@ -70,7 +70,7 @@ module up_delay_cntrl #(
   output                          up_rack);
 
   // internal registers
-  
+
   reg                             up_preset = 'd0;
   reg                             up_wack_int = 'd0;
   reg                             up_rack_int = 'd0;
@@ -128,7 +128,7 @@ module up_delay_cntrl #(
   assign up_rack = (DISABLE == 1) ? 1'd0 : up_rack_int;
   assign up_rdata = (DISABLE == 1) ? 32'd0 : up_rdata_int;
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_preset <= 1'd1;
       up_wack_int <= 'd0;
@@ -167,7 +167,7 @@ module up_delay_cntrl #(
   end
   endgenerate
 
-  // write does not hold- read back what goes into effect. 
+  // write does not hold- read back what goes into effect.
 
   generate
   for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dwr
@@ -180,7 +180,7 @@ module up_delay_cntrl #(
   assign up_dld = (DISABLE == 1) ? 'd0 : up_dld_int;
   assign up_dwdata = (DISABLE == 1) ? 'd0 : up_dwdata_int;
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 0) begin
       up_dld_int <= 'd0;
       up_dwdata_int <= 'd0;

library/common/up_xfer_cntrl.v

@@ -77,7 +77,7 @@ module up_xfer_cntrl #(
   assign up_xfer_done = up_xfer_done_int;
   assign up_xfer_enable_s = up_xfer_state ^ up_xfer_toggle;
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 1'b0) begin
       up_xfer_state_m1 <= 'd0;
       up_xfer_state_m2 <= 'd0;

library/common/up_xfer_status.v

@@ -104,7 +104,7 @@ module up_xfer_status #(
   assign up_data_status = up_data_status_int;
   assign up_xfer_toggle_s = up_xfer_toggle_m3 ^ up_xfer_toggle_m2;
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 1'b0) begin
       up_xfer_toggle_m1 <= 'd0;
       up_xfer_toggle_m2 <= 'd0;

library/xilinx/common/ad_mmcm_drp.v

@@ -94,7 +94,7 @@ module ad_mmcm_drp #(
 
   // drp read and locked
 
-  always @(negedge up_rstn or posedge up_clk) begin
+  always @(posedge up_clk) begin
     if (up_rstn == 1'b0) begin
       up_drp_rdata <= 'd0;
       up_drp_ready <= 'd0;