diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo.v b/library/xilinx/axi_dacfifo/axi_dacfifo.v
index 1360d4a20..eeea7a9c1 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo.v
@@ -130,7 +130,7 @@ module axi_dacfifo #(
   wire                                axi_rd_valid_s;
   wire                                axi_xfer_req_s;
   wire    [31:0]                      axi_last_addr_s;
-  wire    [ 3:0]                      axi_last_beats_s;
+  wire    [ 7:0]                      axi_last_beats_s;
   wire                                axi_dlast_s;
   wire    [ 3:0]                      dma_last_beats_s;
   wire    [(DAC_DATA_WIDTH-1):0]      dac_data_fifo_s;
diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v b/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v
index 47d9ebd9f..3a1909a43 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_rd.v
@@ -46,7 +46,7 @@ module axi_dacfifo_rd #(
 
   input                   axi_xfer_req,
   input       [31:0]      axi_last_raddr,
-  input       [ 3:0]      axi_last_beats,
+  input       [ 7:0]      axi_last_beats,
 
   // axi read address and read data channels
 
@@ -92,7 +92,7 @@ module axi_dacfifo_rd #(
   reg                             axi_ractive = 1'b0;
   reg     [ 31:0]                 axi_araddr_prev = 32'b0;
   reg     [ 1:0]                  axi_xfer_req_m = 2'b0;
-  reg     [ 4:0]                  axi_last_beats_cntr = 16'b0;
+  reg     [ 7:0]                  axi_last_beats_cntr = 8'b0;
 
   // internal signals
 
@@ -100,7 +100,7 @@ module axi_dacfifo_rd #(
   wire                            axi_xfer_req_init;
   wire                            axi_dvalid_s;
   wire                            axi_dlast_s;
-  wire    [ 4:0]                  axi_last_beats_s;
+  wire    [ 8:0]                  axi_last_beats_s;
 
   assign axi_ready_s = (~axi_arvalid | axi_arready) & axi_dready;
 
diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
index 5f4973e84..30a1b43b4 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
@@ -62,7 +62,7 @@ module axi_dacfifo_wr #(
   // syncronization for the read side
 
   output  reg [31:0]      axi_last_addr,
-  output  reg [ 3:0]      axi_last_beats,
+  output  reg [ 7:0]      axi_last_beats,
   output  reg             axi_xfer_out,
 
   // axi write address, write data and write response channels
@@ -142,7 +142,7 @@ module axi_dacfifo_wr #(
 
   reg                                       axi_reset = 1'b0;
   reg                                       axi_xfer_init = 1'b0;
-  reg     [ 3:0]                            axi_wvalid_counter = 4'b0;
+  reg     [ 7:0]                            axi_wvalid_counter = 4'b0;
 
   reg                                       axi_endof_transaction = 1'b0;
   reg                                       axi_endof_transaction_d = 1'b0;
@@ -391,7 +391,7 @@ module axi_dacfifo_wr #(
       axi_mem_last_d <= 1'b0;
       axi_mem_rdata <= 'b0;
       axi_mem_raddr <= 'b0;
-      axi_wvalid_counter <= 4'b0;
+      axi_wvalid_counter <= 8'b0;
       axi_mem_last_read_toggle <= 1'b1;
       axi_mem_raddr_g <= 'b0;
     end else begin
@@ -402,7 +402,7 @@ module axi_dacfifo_wr #(
       axi_mem_rdata <= axi_mem_rdata_s;
       if (axi_mem_rvalid_s == 1'b1) begin
         axi_mem_raddr <= axi_mem_raddr + 1;
-        axi_wvalid_counter <= ((axi_wvalid_counter == axi_awlen) || (axi_xfer_init == 1'b1)) ? 4'b0 : axi_wvalid_counter + 4'b1;
+        axi_wvalid_counter <= ((axi_wvalid_counter == axi_awlen) || (axi_xfer_init == 1'b1)) ? 8'b0 : axi_wvalid_counter + 8'b1;
       end
       if ((axi_endof_transaction == 1'b0) && (axi_endof_transaction_d == 1'b1)) begin
         axi_mem_raddr <= 'b0;
@@ -484,7 +484,7 @@ module axi_dacfifo_wr #(
 
   always @(posedge axi_clk) begin
     if(axi_resetn == 1'b0) begin
-      axi_last_beats <= 4'b0;
+      axi_last_beats <= 8'b0;
     end else begin
       if ((axi_endof_transaction == 1'b1) && (axi_awready == 1'b1) && (axi_awvalid == 1'b1)) begin
         axi_last_beats <= axi_mem_addr_diff;