util_pulse_gen: Optimise design in order to improve timing
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0680e44330
commit
75e4c844ba
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@ -51,7 +51,6 @@ module util_pulse_gen #(
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// internal registers
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reg [(PULSE_WIDTH-1):0] pulse_width_cnt = {PULSE_WIDTH{1'b1}};
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reg [31:0] pulse_period_cnt = 32'h0;
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reg [31:0] pulse_period_read = 32'b0;
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reg [31:0] pulse_width_read = 32'b0;
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@ -82,13 +81,13 @@ module util_pulse_gen #(
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end
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end
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// a free running pulse generator
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// a free running counter
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always @(posedge clk) begin
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if (rstn == 1'b0) begin
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pulse_period_cnt <= PULSE_PERIOD;
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if (pulse_period_cnt == 1'b0) begin
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pulse_period_cnt <= pulse_period_d;
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end else begin
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pulse_period_cnt <= (end_of_period_s) ? pulse_period_d : (pulse_period_cnt - 1'b1);
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pulse_period_cnt <= pulse_period_cnt - 1'b1;
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end
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end
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assign end_of_period_s = (pulse_period_cnt == 32'b0) ? 1'b1 : 1'b0;
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@ -97,14 +96,10 @@ module util_pulse_gen #(
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// generate pulse with a specified width
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always @ (posedge clk) begin
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if (rstn == 1'b0) begin
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pulse <= 1'b0;
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end else if (end_of_period_s) begin
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if (end_of_period_s == 1'b1) begin
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pulse <= 1'b0;
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end else if (pulse_period_cnt == pulse_width_d) begin
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pulse <= 1'b1;
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end else begin
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pulse <= pulse;
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end
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end
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