From 75e4c844baf97ff827dd292e517d33ad41b9b9cd Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 25 Mar 2019 06:46:02 +0000
Subject: [PATCH] util_pulse_gen: Optimise design in order to improve timing

---
 library/common/util_pulse_gen.v | 15 +++++----------
 1 file changed, 5 insertions(+), 10 deletions(-)

diff --git a/library/common/util_pulse_gen.v b/library/common/util_pulse_gen.v
index 7a8cb9f43..c65cbf52e 100644
--- a/library/common/util_pulse_gen.v
+++ b/library/common/util_pulse_gen.v
@@ -51,7 +51,6 @@ module util_pulse_gen #(
 
   // internal registers
 
-  reg     [(PULSE_WIDTH-1):0]  pulse_width_cnt = {PULSE_WIDTH{1'b1}};
   reg     [31:0]               pulse_period_cnt = 32'h0;
   reg     [31:0]               pulse_period_read = 32'b0;
   reg     [31:0]               pulse_width_read = 32'b0;
@@ -82,13 +81,13 @@ module util_pulse_gen #(
     end
   end
 
-  // a free running pulse generator
+  // a free running counter
 
   always @(posedge clk) begin
-    if (rstn == 1'b0) begin
-      pulse_period_cnt <= PULSE_PERIOD;
+    if (pulse_period_cnt == 1'b0) begin
+      pulse_period_cnt <= pulse_period_d;
     end else begin
-      pulse_period_cnt <= (end_of_period_s) ? pulse_period_d : (pulse_period_cnt - 1'b1);
+      pulse_period_cnt <= pulse_period_cnt - 1'b1;
     end
   end
   assign end_of_period_s = (pulse_period_cnt == 32'b0) ? 1'b1 : 1'b0;
@@ -97,14 +96,10 @@ module util_pulse_gen #(
   // generate pulse with a specified width
 
   always @ (posedge clk) begin
-    if (rstn == 1'b0) begin
-      pulse <= 1'b0;
-    end else if (end_of_period_s) begin
+    if (end_of_period_s == 1'b1) begin
       pulse <= 1'b0;
     end else if (pulse_period_cnt == pulse_width_d) begin
       pulse <= 1'b1;
-    end else begin
-      pulse <= pulse;
     end
   end