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util_pulse_gen: Optimise design in order to improve timing

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Istvan Csomortani 2019-03-25 06:46:02 +00:00 committed by István Csomortáni
parent 0680e44330
commit 75e4c844ba
1 changed files with 5 additions and 10 deletions
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15
library/common/util_pulse_gen.v
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@ -51,7 +51,6 @@ module util_pulse_gen #(
// internal registers // internal registers
reg [(PULSE_WIDTH-1):0] pulse_width_cnt = {PULSE_WIDTH{1'b1}};
reg [31:0] pulse_period_cnt = 32'h0; reg [31:0] pulse_period_cnt = 32'h0;
reg [31:0] pulse_period_read = 32'b0; reg [31:0] pulse_period_read = 32'b0;
reg [31:0] pulse_width_read = 32'b0; reg [31:0] pulse_width_read = 32'b0;
@ -82,13 +81,13 @@ module util_pulse_gen #(
end end
end end
// a free running pulse generator // a free running counter
always @(posedge clk) begin always @(posedge clk) begin
if (rstn == 1'b0) begin if (pulse_period_cnt == 1'b0) begin
pulse_period_cnt <= PULSE_PERIOD; pulse_period_cnt <= pulse_period_d;
end else begin end else begin
pulse_period_cnt <= (end_of_period_s) ? pulse_period_d : (pulse_period_cnt - 1'b1); pulse_period_cnt <= pulse_period_cnt - 1'b1;
end end
end end
assign end_of_period_s = (pulse_period_cnt == 32'b0) ? 1'b1 : 1'b0; assign end_of_period_s = (pulse_period_cnt == 32'b0) ? 1'b1 : 1'b0;
@ -97,14 +96,10 @@ module util_pulse_gen #(
// generate pulse with a specified width // generate pulse with a specified width
always @ (posedge clk) begin always @ (posedge clk) begin
if (rstn == 1'b0) begin if (end_of_period_s == 1'b1) begin
pulse <= 1'b0;
end else if (end_of_period_s) begin
pulse <= 1'b0; pulse <= 1'b0;
end else if (pulse_period_cnt == pulse_width_d) begin end else if (pulse_period_cnt == pulse_width_d) begin
pulse <= 1'b1; pulse <= 1'b1;
end else begin
pulse <= pulse;
end end
end end