prcfg_zc706: Update data width and project script
Istvan Csomortani
parent
42874bfe81
commit
766589637e
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@ -45,6 +45,7 @@ if { $runSynth == 1 } {
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set prcfg_name "bist"
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prcfg_synth_reconf $prcfg_name [list "../common/prcfg_system_top.v" \
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"${ad_hdl_dir}/library/prcfg/common/prcfg_top.v" \
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"${ad_hdl_dir}/library/common/ad_pnmon.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_dac.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_adc.v"]
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@ -52,26 +53,26 @@ if { $runSynth == 1 } {
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set prcfg_name "qpsk"
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prcfg_synth_reconf $prcfg_name [list "../common/prcfg_system_top.v" \
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"${ad_hdl_dir}/library/prcfg/common/prcfg_top.v" \
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"${ad_hdl_dir}/library/common/ad_pnmon.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_dac.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_adc.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/qpsk_mod.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/qpsk_demod.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/QPSK_Modulator.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/QPSK_Modulator_Baseband.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/QPSK_Demodulator_Baseband.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/FIR_Interpolation.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/FIR_Decimation.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/Raised_Cosine_Tx_Filter.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/Raised_Cosine_Rx_Filter.v"]
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/Raised_Cosine_Transmit_Filter.v" \
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"${ad_hdl_dir}/library/prcfg/${prcfg_name}/Raised_Cosine_Receive_Filter.v"]
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}
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###############################################################################
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#### IMPLEMENTATION ####
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###############################################################################
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if { $runImpl == 1 } {
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prcfg_impl "prcfg_constr.xdc" [list "default" \
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"bist" \
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"qpsk"]
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prcfg_impl "prcfg_constr.xdc" [list "qpsk" \
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"bist" \
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"default"]
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}
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###############################################################################
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@ -170,13 +170,12 @@ module system_top (
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wire [48:0] gpio_i;
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wire [48:0] gpio_o;
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wire [48:0] gpio_t;
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wire [16:0] gpio_wire;
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wire clk;
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wire dma_dac_dunf;
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wire core_dac_dunf;
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wire [127:0] dma_dac_ddata;
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wire [127:0] core_dac_ddata;
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wire [63:0] dma_dac_ddata;
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wire [63:0] core_dac_ddata;
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wire dma_dac_en;
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wire core_dac_en;
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wire dma_dac_dvalid;
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@ -184,8 +183,8 @@ module system_top (
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wire dma_adc_ovf;
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wire core_adc_ovf;
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wire [127:0] dma_adc_ddata;
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wire [127:0] core_adc_ddata;
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wire [63:0] dma_adc_ddata;
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wire [63:0] core_adc_ddata;
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wire dma_adc_dwr;
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wire core_adc_dwr;
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wire dma_adc_dsync;
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@ -197,11 +196,13 @@ module system_top (
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wire [31:0] dac_gpio_input;
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wire [31:0] dac_gpio_output;
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wire [15:0] ps_intrs;
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// instantiations
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ad_iobuf #(.DATA_WIDTH(49)) i_iobuf_gpio_ps7 (
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.dt (gpio_t[48:0]),
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.di (gpio_o[48:0]),
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.do (gpio_i[48:0]),
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ad_iobuf #(.DATA_WIDTH(32)) i_iobuf_gpio_ps7 (
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.dt ({gpio_t[48:32],gpio_t[14:0]}),
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.di ({gpio_o[48:32],gpio_o[14:0]}),
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.do ({gpio_i[48:32],gpio_i[14:0]}),
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.dio ({ gpio_txnrx, // 48
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gpio_enable, // 47
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gpio_resetb, // 46
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@ -209,7 +210,6 @@ module system_top (
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gpio_en_agc, // 44
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gpio_ctl, // 40
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gpio_status, // 32
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gpio_wire, // 15
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gpio_bd})); // 0
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prcfg_system_top i_prcfg_system_top (
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@ -272,7 +272,22 @@ module system_top (
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.ps_intr_0 (ps_intrs[0]),
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.ps_intr_1 (ps_intrs[1]),
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.ps_intr_10 (ps_intrs[10]),
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.ps_intr_11 (ps_intrs[11]),
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.ps_intr_12 (ps_intrs[12]),
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.ps_intr_13 (ps_intrs[13]),
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.ps_intr_2 (ps_intrs[2]),
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.ps_intr_3 (ps_intrs[3]),
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.ps_intr_4 (ps_intrs[4]),
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.ps_intr_5 (ps_intrs[5]),
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.ps_intr_6 (ps_intrs[6]),
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.ps_intr_7 (ps_intrs[7]),
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.ps_intr_8 (ps_intrs[8]),
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.ps_intr_9 (ps_intrs[9]),
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.ad9361_dac_dma_irq (ps_intrs[12]),
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.ad9361_adc_dma_irq (ps_intrs[13]),
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.rx_clk_in_n (rx_clk_in_n),
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.rx_clk_in_p (rx_clk_in_p),
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.rx_data_in_n (rx_data_in_n),
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@ -333,19 +348,19 @@ endmodule
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output [31:0] dac_gpio_output,
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output dma_dac_en,
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input dma_dac_dunf,
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input [127:0] dma_dac_ddata,
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input [63:0] dma_dac_ddata,
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input dma_dac_dvalid,
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input core_dac_en,
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output core_dac_dunf,
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output [127:0] core_dac_ddata,
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output [63:0] core_dac_ddata,
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output core_dac_dvalid,
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input core_adc_dwr,
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input core_adc_dsync,
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input [127:0] core_adc_ddata,
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input [63:0] core_adc_ddata,
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output core_adc_ovf,
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output dma_adc_dwr,
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output dma_adc_dsync,
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output [127:0] dma_adc_ddata,
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output [63:0] dma_adc_ddata,
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input dma_adc_ovf);
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endmodule
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