diff --git a/library/axi_pwm_gen/axi_pwm_gen.v b/library/axi_pwm_gen/axi_pwm_gen.v
index 13ac05efa..3c1dfb83e 100644
--- a/library/axi_pwm_gen/axi_pwm_gen.v
+++ b/library/axi_pwm_gen/axi_pwm_gen.v
@@ -192,7 +192,7 @@ module axi_pwm_gen #(
   // offset counter
 
   always @(posedge clk) begin
-    if (offset_alignment) begin
+    if (offset_alignment ==  1'b1 || pwm_gen_resetn == 1'b0) begin
       offset_cnt <= 32'd0;
     end else begin
       offset_cnt <= offset_cnt + 1'b1;
diff --git a/library/axi_pwm_gen/axi_pwm_gen_1.v b/library/axi_pwm_gen/axi_pwm_gen_1.v
index f44da7d80..690b3aa8f 100644
--- a/library/axi_pwm_gen/axi_pwm_gen_1.v
+++ b/library/axi_pwm_gen/axi_pwm_gen_1.v
@@ -55,10 +55,10 @@ module axi_pwm_gen_1 #(
   // internal registers
 
   reg     [31:0]               pulse_period_cnt = 32'h0;
-  reg     [31:0]               pulse_period_read = 32'b0;
-  reg     [31:0]               pulse_width_read = 32'b0;
-  reg     [31:0]               pulse_period_d = 32'b0;
-  reg     [31:0]               pulse_width_d = 32'b0;
+  reg     [31:0]               pulse_period_read =  PULSE_PERIOD;
+  reg     [31:0]               pulse_width_read = PULSE_WIDTH;
+  reg     [31:0]               pulse_period_d = PULSE_PERIOD;
+  reg     [31:0]               pulse_width_d = PULSE_WIDTH;
   reg                          phase_align_armed = 1'b1;
 
   // internal wires
@@ -76,10 +76,10 @@ module axi_pwm_gen_1 #(
 
   always @(posedge clk) begin
     if (rstn == 1'b0) begin
-      pulse_period_d <= PULSE_PERIOD;
-      pulse_width_d <= PULSE_WIDTH;
-      pulse_period_read <= PULSE_PERIOD;
-      pulse_width_read <= PULSE_WIDTH;
+      pulse_period_d <= pulse_period;
+      pulse_width_d <= pulse_width;
+      pulse_period_read <= pulse_period;
+      pulse_width_read <= pulse_width;
     end else begin
       // load the input period/width values
       if (load_config) begin
diff --git a/library/axi_pwm_gen/axi_pwm_gen_regmap.v b/library/axi_pwm_gen/axi_pwm_gen_regmap.v
index 0fc087a50..0f74c49cd 100644
--- a/library/axi_pwm_gen/axi_pwm_gen_regmap.v
+++ b/library/axi_pwm_gen/axi_pwm_gen_regmap.v
@@ -98,7 +98,7 @@ module axi_pwm_gen_regmap #(
   reg     [31:0]  up_pwm_offset_2 = PULSE_2_OFFSET;
   reg     [31:0]  up_pwm_offset_3 = PULSE_3_OFFSET;
   reg             up_load_config = 1'b0;
-  reg             up_reset;
+  reg             up_reset = 1'b1;
 
   always @(posedge up_clk) begin
     if (up_rstn == 0) begin