From 7732a365b542e146e3db78e4daa60e30e2f7b975 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Sat, 15 Aug 2020 11:24:27 +0300
Subject: [PATCH] Revert "axi_spi_engine: Add pulse_width and pulse_period
 registers"

This reverts commit 0402ce85e470343b7b58d678eec964774126c882
and reverts commit 164aa97ec30c8cada72bf7f7989af42f716670b3.

The trigger pulse generation must be handled outside of the
SPI Engine framework.

It is recommanded to be done in system level using a PWM
generator or an external signal.
---
 .../axi_spi_engine/axi_spi_engine.v           | 23 +------------------
 1 file changed, 1 insertion(+), 22 deletions(-)

diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine.v b/library/spi_engine/axi_spi_engine/axi_spi_engine.v
index 95d1051dc..d2491ade6 100644
--- a/library/spi_engine/axi_spi_engine/axi_spi_engine.v
+++ b/library/spi_engine/axi_spi_engine/axi_spi_engine.v
@@ -125,13 +125,7 @@ module axi_spi_engine #(
 
   output offload_sync_ready,
   input offload_sync_valid,
-  input [7:0] offload_sync_data,
-
-  // Configuration interface conversion start generator (PWM)
-
-  output reg [31:0] pulse_gen_period,
-  output reg [31:0] pulse_gen_width,
-  output reg pulse_gen_load);
+  input [7:0] offload_sync_data);
 
   localparam PCORE_VERSION = 'h010071;
   localparam S_AXI = 0;
@@ -298,31 +292,18 @@ module axi_spi_engine #(
   reg offload0_mem_reset_reg;
   wire offload0_enabled_s;
 
-
-  always @(posedge clk) begin
-    if ((up_waddr_s == 8'h48) && (up_wreq_s == 1'b1)) begin
-      pulse_gen_load <= 1'b1;
-    end else begin
-      pulse_gen_load <= 1'b0;
-    end
-  end
-
   // the software reset should reset all the registers
   always @(posedge clk) begin
     if (up_sw_resetn == 1'b0) begin
       up_irq_mask <= 'h00;
       offload0_enable_reg <= 1'b0;
       offload0_mem_reset_reg <= 1'b0;
-      pulse_gen_period <= 32'h0;
-      pulse_gen_width <= 32'h0;
     end else begin
       if (up_wreq_s) begin
         case (up_waddr_s)
           8'h20: up_irq_mask <= up_wdata_s;
           8'h40: offload0_enable_reg <= up_wdata_s[0];
           8'h42: offload0_mem_reset_reg <= up_wdata_s[0];
-          8'h48: pulse_gen_period <= up_wdata_s;
-          8'h49: pulse_gen_width <= up_wdata_s;
         endcase
       end
     end
@@ -365,8 +346,6 @@ module axi_spi_engine #(
       8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */
       8'h40: up_rdata_ff <= {offload0_enable_reg};
       8'h41: up_rdata_ff <= {offload0_enabled_s};
-      8'h48: up_rdata_ff <= pulse_gen_period;
-      8'h49: up_rdata_ff <= pulse_gen_width;
       default: up_rdata_ff <= 'h00;
     endcase
   end