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Revert "axi_spi_engine: Add pulse_width and pulse_period registers" 

This reverts commit 0402ce85e4
and reverts commit 164aa97ec3.

The trigger pulse generation must be handled outside of the
SPI Engine framework.

It is recommanded to be done in system level using a PWM
generator or an external signal.
main
Istvan Csomortani 2020-08-15 11:24:27 +03:00 committed by István Csomortáni
parent 37254358dd
commit 7732a365b5
1 changed files with 1 additions and 22 deletions
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23
library/spi_engine/axi_spi_engine/axi_spi_engine.v
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@ -125,13 +125,7 @@ module axi_spi_engine #(
output offload_sync_ready, output offload_sync_ready,
input offload_sync_valid, input offload_sync_valid,
input [7:0] offload_sync_data, input [7:0] offload_sync_data);
// Configuration interface conversion start generator (PWM)
output reg [31:0] pulse_gen_period,
output reg [31:0] pulse_gen_width,
output reg pulse_gen_load);
localparam PCORE_VERSION = 'h010071; localparam PCORE_VERSION = 'h010071;
localparam S_AXI = 0; localparam S_AXI = 0;
@ -298,31 +292,18 @@ module axi_spi_engine #(
reg offload0_mem_reset_reg; reg offload0_mem_reset_reg;
wire offload0_enabled_s; wire offload0_enabled_s;
always @(posedge clk) begin
if ((up_waddr_s == 8'h48) && (up_wreq_s == 1'b1)) begin
pulse_gen_load <= 1'b1;
end else begin
pulse_gen_load <= 1'b0;
end
end
// the software reset should reset all the registers // the software reset should reset all the registers
always @(posedge clk) begin always @(posedge clk) begin
if (up_sw_resetn == 1'b0) begin if (up_sw_resetn == 1'b0) begin
up_irq_mask <= 'h00; up_irq_mask <= 'h00;
offload0_enable_reg <= 1'b0; offload0_enable_reg <= 1'b0;
offload0_mem_reset_reg <= 1'b0; offload0_mem_reset_reg <= 1'b0;
pulse_gen_period <= 32'h0;
pulse_gen_width <= 32'h0;
end else begin end else begin
if (up_wreq_s) begin if (up_wreq_s) begin
case (up_waddr_s) case (up_waddr_s)
8'h20: up_irq_mask <= up_wdata_s; 8'h20: up_irq_mask <= up_wdata_s;
8'h40: offload0_enable_reg <= up_wdata_s[0]; 8'h40: offload0_enable_reg <= up_wdata_s[0];
8'h42: offload0_mem_reset_reg <= up_wdata_s[0]; 8'h42: offload0_mem_reset_reg <= up_wdata_s[0];
8'h48: pulse_gen_period <= up_wdata_s;
8'h49: pulse_gen_width <= up_wdata_s;
endcase endcase
end end
end end
@ -365,8 +346,6 @@ module axi_spi_engine #(
8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */ 8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */
8'h40: up_rdata_ff <= {offload0_enable_reg}; 8'h40: up_rdata_ff <= {offload0_enable_reg};
8'h41: up_rdata_ff <= {offload0_enabled_s}; 8'h41: up_rdata_ff <= {offload0_enabled_s};
8'h48: up_rdata_ff <= pulse_gen_period;
8'h49: up_rdata_ff <= pulse_gen_width;
default: up_rdata_ff <= 'h00; default: up_rdata_ff <= 'h00;
endcase endcase
end end