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up_adc_channel: Update IPs and adi_regmap_adc definition file to latest up_adc_channel module

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alin724 2022-09-12 18:51:08 +03:00 committed by Alin-Tudor Sferle
parent 045327c8db
commit 775a23ebf2
15 changed files with 63 additions and 12 deletions
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15
docs/regmap/adi_regmap_adc.txt
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@ -713,6 +713,21 @@ it indicates an over range over a data transfer period. Software must first clea
this bit before initiating a transfer and monitor afterwards.
ENDFIELD
############################################################################################
############################################################################################
REG
0x0102
REG_CHAN_RAW_DATA
ADC Raw Data Reading
ENDREG
FIELD
[31:0] 0x0000
ADC_READ_DATA[31:0]
RO
Raw data read from the ADC.
ENDFIELD
############################################################################################
############################################################################################

1
library/axi_ad7768/axi_ad7768.v
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@ -203,6 +203,7 @@ module axi_ad7768 #(
.adc_pn_err (1'b0),
.adc_pn_oos (1'b0),
.adc_or (1'b0),
.adc_read_data ('d0),
.adc_status_header(adc_status_header[i]),
.adc_crc_err(adc_crc_err[i]),
.up_adc_pn_err (),

1
library/axi_ad777x/axi_ad777x.v
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@ -202,6 +202,7 @@ module axi_ad777x #(
.adc_pn_err (1'b0),
.adc_pn_oos (1'b0),
.adc_or (1'b0),
.adc_read_data ('d0),
.adc_status_header(adc_status_header[i]),
.adc_crc_err(adc_crc_err[i]),
.up_adc_pn_err (),

5
library/axi_ad9265/axi_ad9265_channel.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -153,6 +153,9 @@ module axi_ad9265_channel #(
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.adc_read_data ('d0),
.adc_status_header ('d0),
.adc_crc_err ('d0),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),

5
library/axi_ad9361/axi_ad9361_rx_channel.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -204,6 +204,9 @@ module axi_ad9361_rx_channel #(
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.adc_read_data ('d0),
.adc_status_header ('d0),
.adc_crc_err ('d0),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),

5
library/axi_ad9434/axi_ad9434_core.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -237,6 +237,9 @@ module axi_ad9434_core #(
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.adc_read_data ('d0),
.adc_status_header ('d0),
.adc_crc_err ('d0),
.up_adc_pn_err (up_status_pn_err_s),
.up_adc_pn_oos (up_status_pn_oos_s),
.up_adc_or (up_status_or_s),

5
library/axi_ad9467/axi_ad9467_channel.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -124,6 +124,9 @@ module axi_ad9467_channel#(
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.adc_read_data ('d0),
.adc_status_header ('d0),
.adc_crc_err ('d0),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),

5
library/axi_ad9625/axi_ad9625_channel.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -126,6 +126,9 @@ module axi_ad9625_channel (
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.adc_read_data ('d0),
.adc_status_header ('d0),
.adc_crc_err ('d0),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),

5
library/axi_ad9671/axi_ad9671_channel.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -123,6 +123,9 @@ module axi_ad9671_channel #(
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.adc_read_data ('d0),
.adc_status_header ('d0),
.adc_crc_err ('d0),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),

5
library/axi_ad9684/axi_ad9684_channel.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -136,6 +136,9 @@ module axi_ad9684_channel #(
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.adc_read_data ('d0),
.adc_status_header ('d0),
.adc_crc_err ('d0),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),

5
library/axi_ad9963/axi_ad9963_rx_channel.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -189,6 +189,9 @@ module axi_ad9963_rx_channel #(
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.adc_read_data ('d0),
.adc_status_header ('d0),
.adc_crc_err ('d0),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),

3
library/axi_adaq8092/axi_adaq8092_channel.v
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@ -139,6 +139,9 @@ module axi_adaq8092_channel #(
.adc_pn_err (),
.adc_pn_oos (),
.adc_or (adc_or),
.adc_read_data ('d0),
.adc_status_header ('d0),
.adc_crc_err ('d0),
.up_adc_pn_err (),
.up_adc_pn_oos (),
.up_adc_or (up_adc_or),

5
library/axi_adrv9001/axi_adrv9001_rx_channel.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -290,6 +290,9 @@ module axi_adrv9001_rx_channel #(
.adc_pn_err (adc_pn_err_s & valid_seq_sel),
.adc_pn_oos (adc_pn_oos_s & valid_seq_sel),
.adc_or (1'd0),
.adc_read_data ('d0),
.adc_status_header ('d0),
.adc_crc_err ('d0),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),

5
library/axi_generic_adc/axi_generic_adc.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -218,6 +218,9 @@ module axi_generic_adc #(
.adc_pn_err (1'b0),
.adc_pn_oos (1'b0),
.adc_or (1'b0),
.adc_read_data ('d0),
.adc_status_header ('d0),
.adc_crc_err ('d0),
.up_adc_pn_err (),
.up_adc_pn_oos (),
.up_adc_or (),

5
library/axi_ltc2387/axi_ltc2387_channel.v
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@ -176,8 +176,9 @@ module axi_ltc2387_channel #(
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (1'b0),
.adc_or (1'b0),
.adc_status_header (8'd0),
.adc_crc_err (1'b0),
.adc_read_data ('d0),
.adc_status_header ('d0),
.adc_crc_err ('d0),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),