axi_dmac: Make debug register optional

The debug registers are useful during development but are rarely used in a
production design. Add a option that allows to disable them, this reduces
the resource utilization of the DMAC.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

library/axi_dmac/axi_dmac.v

@@ -199,6 +199,8 @@ parameter DMA_TYPE_SRC = 2;
 parameter MAX_BYTES_PER_BURST = 128;
 parameter FIFO_SIZE = 4; // In bursts
 
+parameter DISABLE_DEBUG_REGISTERS = 0;
+
 localparam DMA_TYPE_AXI_MM = 0;
 localparam DMA_TYPE_AXI_STREAM = 1;
 localparam DMA_TYPE_FIFO = 2;
@@ -289,6 +291,7 @@ wire [ID_WIDTH-1:0] src_data_id;
 wire [ID_WIDTH-1:0] src_address_id;
 wire [ID_WIDTH-1:0] src_response_id;
 wire [7:0] dbg_status;
+wire [31:0] dbg_ids;
 
 assign m_dest_axi_araddr = 'd0;
 assign m_dest_axi_arlen = 'd0;
@@ -409,6 +412,12 @@ begin
   end
 end
 
+assign dbg_ids = {
+  src_response_id, 1'b0, src_data_id, 1'b0, src_address_id, 1'b0,
+  src_request_id, 1'b0, dest_response_id, 1'b0, dest_data_id, 1'b0,
+  dest_address_id, 1'b0, dest_request_id
+};
+
 always @(posedge s_axi_aclk)
 begin
   if (s_axi_aresetn == 1'b0) begin
@@ -437,11 +446,10 @@ begin
     12'h10a: up_rdata <= up_transfer_done_bitmap;
     12'h10b: up_rdata <= up_transfer_id_eot;
     12'h10c: up_rdata <= 'h00; // Status
-    12'h10d: up_rdata <= m_dest_axi_awaddr; //HAS_DEST_ADDR ? 'h00 : 'h00; // Current dest address
-    12'h10e: up_rdata <= m_src_axi_araddr; //HAS_SRC_ADDR ? 'h00 : 'h00; // Current src address
-    12'h10f: up_rdata <= {src_response_id, 1'b0, src_data_id, 1'b0, src_address_id, 1'b0, src_request_id,
-              1'b0, dest_response_id, 1'b0, dest_data_id, 1'b0, dest_address_id, 1'b0, dest_request_id};
-    12'h110: up_rdata <= dbg_status;
+    12'h10d: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : m_dest_axi_awaddr; //HAS_DEST_ADDR ? 'h00 : 'h00; // Current dest address
+    12'h10e: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : m_src_axi_araddr; //HAS_SRC_ADDR ? 'h00 : 'h00; // Current src address
+    12'h10f: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_ids;
+    12'h110: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_status;
     default: up_rdata <= 'h00;
     endcase
   end

library/axi_dmac/axi_dmac_constr.ttcl

@@ -6,6 +6,7 @@
 <: set async_dest_req [getBooleanValue "ASYNC_CLK_DEST_REQ"] :>
 <: set async_req_src [getBooleanValue "ASYNC_CLK_REQ_SRC"] :>
 <: set async_src_dest [getBooleanValue "ASYNC_CLK_SRC_DEST"] :>
+<: set disable_debug_registers [getBooleanValue "DISABLE_DEBUG_REGISTERS"] :>
 
 set req_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
 set src_clk [get_clocks -of_objects [get_ports -quiet {fifo_wr_clk s_axis_aclk m_src_axi_aclk}]]
@@ -151,6 +152,7 @@ set_false_path -quiet \
 	-to [get_pins -quiet -hier *reset_shift_reg*/PRE]
 
 # Ignore timing for debug signals to register map
+<: if {!$disable_debug_registers} { :>
 set_false_path -quiet \
 	-from [get_cells -quiet -hier *cdc_sync_stage2_reg* \
 		-filter {name =~ *i_sync_src_request_id* && IS_SEQUENTIAL}] \
@@ -165,3 +167,4 @@ set_false_path -quiet \
 set_false_path -quiet \
 	-from [get_cells -quiet -hier *address_reg* -filter {name =~ *i_addr_gen* && IS_SEQUENTIAL}] \
 	-to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}]
+<: } :>

library/axi_dmac/axi_dmac_ip.tcl

@@ -178,6 +178,7 @@ foreach {k v} { \
 		"SYNC_TRANSFER_START" "false" \
 		"AXI_SLICE_SRC" "false" \
 		"AXI_SLICE_DEST" "false" \
+		"DISABLE_DEBUG_REGISTERS" "false" \
 	} { \
 	set_property -dict [list \
 			"value_format" "bool" \
@@ -327,5 +328,14 @@ set_property -dict [list \
 	"display_name" "Destination and Request Clock Asynchronous" \
 ] $p
 
+set dbg_group [ipgui::add_group -name {Debug} -component $cc \
+		-parent $page0 -display_name {Debug}]
+
+set p [ipgui::get_guiparamspec -name "DISABLE_DEBUG_REGISTERS" -component $cc]
+ipgui::move_param -component $cc -order 0 $p -parent $dbg_group
+set_property -dict [list \
+	"display_name" "Disable Debug Registers" \
+] $p
+
 ipx::create_xgui_files [ipx::current_core]
 ipx::save_core $cc