From 782b27e894821641afe77b1a1906a382e9aee7f1 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 1 Feb 2022 11:50:16 +0200 Subject: [PATCH] DAC DDS: Add support for DDS phase width > 16 Add support for DDS phase width greather than 16. The software should read the DDS phase data width register and configure the DDS init and increment registers accordingly, otherwise the obtained DDS output frequency will not be the desired one for DDS phase width different than 16. DDS_incr = (f_out * 2^(phase_width) * clkratio)/f_if --- library/common/ad_dds.v | 6 +-- library/common/up_dac_channel.v | 80 ++++++++++++++++++++++++++++----- library/common/up_dac_common.v | 2 +- 3 files changed, 72 insertions(+), 16 deletions(-) diff --git a/library/common/ad_dds.v b/library/common/ad_dds.v index 59670df41..2aa408143 100644 --- a/library/common/ad_dds.v +++ b/library/common/ad_dds.v @@ -41,7 +41,7 @@ module ad_dds #( parameter DISABLE = 0, // range 8-24 parameter DDS_DW = 16, - // range 8-16 (FIX ME) + // range 8-32 parameter PHASE_DW = 16, // set 1 for CORDIC or 2 for Polynomial parameter DDS_TYPE = 1, @@ -62,8 +62,8 @@ module ad_dds #( input dac_valid, input [ 15:0] tone_1_scale, input [ 15:0] tone_2_scale, - input [ 15:0] tone_1_init_offset, - input [ 15:0] tone_2_init_offset, + input [ PHASE_DW-1:0] tone_1_init_offset, + input [ PHASE_DW-1:0] tone_2_init_offset, input [ PHASE_DW-1:0] tone_1_freq_word, input [ PHASE_DW-1:0] tone_2_freq_word, output reg [DDS_DW*CLK_RATIO-1:0] dac_dds_data diff --git a/library/common/up_dac_channel.v b/library/common/up_dac_channel.v index eddd19eb5..94b1787d4 100644 --- a/library/common/up_dac_channel.v +++ b/library/common/up_dac_channel.v @@ -43,6 +43,7 @@ module up_dac_channel #( parameter CHANNEL_ID = 4'h0, parameter CHANNEL_NUMBER = 8'b0, parameter DDS_DISABLE = 0, + parameter DDS_PHASE_DW = 16, parameter USERPORTS_DISABLE = 0, parameter IQCORRECTION_DISABLE = 0, parameter XBAR_ENABLE = 0 @@ -53,11 +54,11 @@ module up_dac_channel #( input dac_clk, input dac_rst, output [15:0] dac_dds_scale_1, - output [15:0] dac_dds_init_1, - output [15:0] dac_dds_incr_1, output [15:0] dac_dds_scale_2, - output [15:0] dac_dds_init_2, - output [15:0] dac_dds_incr_2, + output [DDS_PHASE_DW-1:0] dac_dds_init_1, + output [DDS_PHASE_DW-1:0] dac_dds_incr_1, + output [DDS_PHASE_DW-1:0] dac_dds_init_2, + output [DDS_PHASE_DW-1:0] dac_dds_incr_2, output [15:0] dac_pat_data_1, output [15:0] dac_pat_data_2, output [ 3:0] dac_data_sel, @@ -108,6 +109,10 @@ module up_dac_channel #( reg [15:0] up_dac_dds_scale_2 = 'd0; reg [15:0] up_dac_dds_init_2 = 'd0; reg [15:0] up_dac_dds_incr_2 = 'd0; + reg [15:0] up_dac_dds_init_1_extend = 'd0; + reg [15:0] up_dac_dds_incr_1_extend = 'd0; + reg [15:0] up_dac_dds_init_2_extend = 'd0; + reg [15:0] up_dac_dds_incr_2_extend = 'd0; reg [15:0] up_dac_pat_data_2 = 'd0; reg [15:0] up_dac_pat_data_1 = 'd0; reg up_dac_iqcor_enb = 'd0; @@ -136,8 +141,18 @@ module up_dac_channel #( // internal signals - wire up_wreq_s; - wire up_rreq_s; + wire up_wreq_s; + wire up_rreq_s; + wire [ 5:0] dds_phase_w = DDS_PHASE_DW[5:0]; + + wire [15:0] dac_dds_init_1_s; + wire [15:0] dac_dds_incr_1_s; + wire [15:0] dac_dds_init_2_s; + wire [15:0] dac_dds_incr_2_s; + wire [15:0] dac_dds_init_1_extend; + wire [15:0] dac_dds_incr_1_extend; + wire [15:0] dac_dds_init_2_extend; + wire [15:0] dac_dds_incr_2_extend; // 2's complement function @@ -180,6 +195,10 @@ module up_dac_channel #( up_dac_dds_scale_2 <= 'd0; up_dac_dds_init_2 <= 'd0; up_dac_dds_incr_2 <= 'd0; + up_dac_dds_init_1_extend <= 'd0; + up_dac_dds_incr_1_extend <= 'd0; + up_dac_dds_init_2_extend <= 'd0; + up_dac_dds_incr_2_extend <= 'd0; end end else begin always @(negedge up_rstn or posedge up_clk) begin @@ -190,6 +209,10 @@ module up_dac_channel #( up_dac_dds_scale_2 <= 'd0; up_dac_dds_init_2 <= 'd0; up_dac_dds_incr_2 <= 'd0; + up_dac_dds_init_1_extend <= 'd0; + up_dac_dds_incr_1_extend <= 'd0; + up_dac_dds_init_2_extend <= 'd0; + up_dac_dds_incr_2_extend <= 'd0; end else begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin up_dac_dds_scale_1 <= up_wdata[15:0]; @@ -205,6 +228,14 @@ module up_dac_channel #( up_dac_dds_init_2 <= up_wdata[31:16]; up_dac_dds_incr_2 <= up_wdata[15:0]; end + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hb)) begin + up_dac_dds_init_1_extend <= up_wdata[31:16]; + up_dac_dds_incr_1_extend <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hc)) begin + up_dac_dds_init_2_extend <= up_wdata[31:16]; + up_dac_dds_incr_2_extend <= up_wdata[15:0]; + end end end end @@ -350,7 +381,7 @@ module up_dac_channel #( up_rack_int <= up_rreq_s; if (up_rreq_s == 1'b1) begin case (up_raddr[3:0]) - 4'h0: up_rdata_int <= { 16'd0, up_dac_dds_scale_1}; + 4'h0: up_rdata_int <= { 10'd0, dds_phase_w, up_dac_dds_scale_1}; 4'h1: up_rdata_int <= { up_dac_dds_init_1, up_dac_dds_incr_1}; 4'h2: up_rdata_int <= { 16'd0, up_dac_dds_scale_2}; 4'h3: up_rdata_int <= { up_dac_dds_init_2, up_dac_dds_incr_2}; @@ -363,6 +394,8 @@ module up_dac_channel #( dac_usr_datatype_bits}; 4'h9: up_rdata_int <= { dac_usr_interpolation_m, dac_usr_interpolation_n}; 4'ha: up_rdata_int <= { 30'd0, up_dac_iq_mode}; + 4'hb: up_rdata_int <= { up_dac_dds_init_1_extend, up_dac_dds_incr_1_extend}; + 4'hc: up_rdata_int <= { up_dac_dds_init_2_extend, up_dac_dds_incr_2_extend}; default: up_rdata_int <= 0; endcase end else begin @@ -404,7 +437,7 @@ module up_dac_channel #( // dac control & status up_xfer_cntrl #( - .DATA_WIDTH(177) + .DATA_WIDTH(240) ) i_xfer_cntrl ( .up_rstn (up_rstn), .up_clk (up_clk), @@ -418,6 +451,10 @@ module up_dac_channel #( up_dac_dds_scale_tc_2, up_dac_dds_init_2, up_dac_dds_incr_2, + up_dac_dds_init_1_extend, + up_dac_dds_incr_1_extend, + up_dac_dds_init_2_extend, + up_dac_dds_incr_2_extend, up_dac_pat_data_1, up_dac_pat_data_2, up_dac_data_sel_m, @@ -431,15 +468,34 @@ module up_dac_channel #( dac_iqcor_coeff_1, dac_iqcor_coeff_2, dac_dds_scale_1, - dac_dds_init_1, - dac_dds_incr_1, + dac_dds_init_1_s, + dac_dds_incr_1_s, dac_dds_scale_2, - dac_dds_init_2, - dac_dds_incr_2, + dac_dds_init_2_s, + dac_dds_incr_2_s, + dac_dds_init_1_extend, + dac_dds_incr_1_extend, + dac_dds_init_2_extend, + dac_dds_incr_2_extend, dac_pat_data_1, dac_pat_data_2, dac_data_sel, dac_mask_enable, dac_src_chan_sel})); +generate +if (DDS_PHASE_DW > 16) begin + localparam DDS_EXT_DW = DDS_PHASE_DW - 16 - 1; + assign dac_dds_init_1 = {dac_dds_init_1_extend[DDS_EXT_DW:0], dac_dds_init_1_s}; + assign dac_dds_incr_1 = {dac_dds_incr_1_extend[DDS_EXT_DW:0], dac_dds_incr_1_s}; + assign dac_dds_init_2 = {dac_dds_init_2_extend[DDS_EXT_DW:0], dac_dds_init_2_s}; + assign dac_dds_incr_2 = {dac_dds_incr_2_extend[DDS_EXT_DW:0], dac_dds_incr_2_s}; +end else begin + assign dac_dds_init_1 = dac_dds_init_1_s[DDS_PHASE_DW-1:0]; + assign dac_dds_incr_1 = dac_dds_incr_1_s[DDS_PHASE_DW-1:0]; + assign dac_dds_init_2 = dac_dds_init_2_s[DDS_PHASE_DW-1:0]; + assign dac_dds_incr_2 = dac_dds_incr_2_s[DDS_PHASE_DW-1:0]; +end +endgenerate + endmodule diff --git a/library/common/up_dac_common.v b/library/common/up_dac_common.v index 1e4f29c81..4f284a77a 100644 --- a/library/common/up_dac_common.v +++ b/library/common/up_dac_common.v @@ -118,7 +118,7 @@ module up_dac_common #( // parameters - localparam VERSION = 32'h00090162; + localparam VERSION = 32'h00090262; // internal registers