DAC DDS: Add support for DDS phase width > 16
Add support for DDS phase width greather than 16. The software should read the DDS phase data width register and configure the DDS init and increment registers accordingly, otherwise the obtained DDS output frequency will not be the desired one for DDS phase width different than 16. DDS_incr = (f_out * 2^(phase_width) * clkratio)/f_ifmain
AndreiGrozav
AndreiGrozav
parent
f5184b4e14
commit
782b27e894
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@ -41,7 +41,7 @@ module ad_dds #(
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parameter DISABLE = 0,
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// range 8-24
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parameter DDS_DW = 16,
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// range 8-16 (FIX ME)
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// range 8-32
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parameter PHASE_DW = 16,
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// set 1 for CORDIC or 2 for Polynomial
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parameter DDS_TYPE = 1,
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@ -62,8 +62,8 @@ module ad_dds #(
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input dac_valid,
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input [ 15:0] tone_1_scale,
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input [ 15:0] tone_2_scale,
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input [ 15:0] tone_1_init_offset,
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input [ 15:0] tone_2_init_offset,
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input [ PHASE_DW-1:0] tone_1_init_offset,
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input [ PHASE_DW-1:0] tone_2_init_offset,
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input [ PHASE_DW-1:0] tone_1_freq_word,
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input [ PHASE_DW-1:0] tone_2_freq_word,
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output reg [DDS_DW*CLK_RATIO-1:0] dac_dds_data
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@ -43,6 +43,7 @@ module up_dac_channel #(
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parameter CHANNEL_ID = 4'h0,
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parameter CHANNEL_NUMBER = 8'b0,
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parameter DDS_DISABLE = 0,
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parameter DDS_PHASE_DW = 16,
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parameter USERPORTS_DISABLE = 0,
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parameter IQCORRECTION_DISABLE = 0,
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parameter XBAR_ENABLE = 0
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@ -53,11 +54,11 @@ module up_dac_channel #(
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input dac_clk,
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input dac_rst,
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output [15:0] dac_dds_scale_1,
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output [15:0] dac_dds_init_1,
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output [15:0] dac_dds_incr_1,
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output [15:0] dac_dds_scale_2,
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output [15:0] dac_dds_init_2,
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output [15:0] dac_dds_incr_2,
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output [DDS_PHASE_DW-1:0] dac_dds_init_1,
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output [DDS_PHASE_DW-1:0] dac_dds_incr_1,
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output [DDS_PHASE_DW-1:0] dac_dds_init_2,
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output [DDS_PHASE_DW-1:0] dac_dds_incr_2,
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output [15:0] dac_pat_data_1,
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output [15:0] dac_pat_data_2,
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output [ 3:0] dac_data_sel,
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@ -108,6 +109,10 @@ module up_dac_channel #(
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reg [15:0] up_dac_dds_scale_2 = 'd0;
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reg [15:0] up_dac_dds_init_2 = 'd0;
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reg [15:0] up_dac_dds_incr_2 = 'd0;
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reg [15:0] up_dac_dds_init_1_extend = 'd0;
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reg [15:0] up_dac_dds_incr_1_extend = 'd0;
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reg [15:0] up_dac_dds_init_2_extend = 'd0;
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reg [15:0] up_dac_dds_incr_2_extend = 'd0;
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reg [15:0] up_dac_pat_data_2 = 'd0;
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reg [15:0] up_dac_pat_data_1 = 'd0;
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reg up_dac_iqcor_enb = 'd0;
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@ -138,6 +143,16 @@ module up_dac_channel #(
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wire up_wreq_s;
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wire up_rreq_s;
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wire [ 5:0] dds_phase_w = DDS_PHASE_DW[5:0];
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wire [15:0] dac_dds_init_1_s;
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wire [15:0] dac_dds_incr_1_s;
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wire [15:0] dac_dds_init_2_s;
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wire [15:0] dac_dds_incr_2_s;
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wire [15:0] dac_dds_init_1_extend;
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wire [15:0] dac_dds_incr_1_extend;
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wire [15:0] dac_dds_init_2_extend;
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wire [15:0] dac_dds_incr_2_extend;
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// 2's complement function
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@ -180,6 +195,10 @@ module up_dac_channel #(
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up_dac_dds_scale_2 <= 'd0;
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up_dac_dds_init_2 <= 'd0;
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up_dac_dds_incr_2 <= 'd0;
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up_dac_dds_init_1_extend <= 'd0;
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up_dac_dds_incr_1_extend <= 'd0;
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up_dac_dds_init_2_extend <= 'd0;
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up_dac_dds_incr_2_extend <= 'd0;
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end
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end else begin
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always @(negedge up_rstn or posedge up_clk) begin
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@ -190,6 +209,10 @@ module up_dac_channel #(
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up_dac_dds_scale_2 <= 'd0;
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up_dac_dds_init_2 <= 'd0;
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up_dac_dds_incr_2 <= 'd0;
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up_dac_dds_init_1_extend <= 'd0;
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up_dac_dds_incr_1_extend <= 'd0;
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up_dac_dds_init_2_extend <= 'd0;
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up_dac_dds_incr_2_extend <= 'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
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up_dac_dds_scale_1 <= up_wdata[15:0];
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@ -205,6 +228,14 @@ module up_dac_channel #(
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up_dac_dds_init_2 <= up_wdata[31:16];
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up_dac_dds_incr_2 <= up_wdata[15:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hb)) begin
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up_dac_dds_init_1_extend <= up_wdata[31:16];
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up_dac_dds_incr_1_extend <= up_wdata[15:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hc)) begin
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up_dac_dds_init_2_extend <= up_wdata[31:16];
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up_dac_dds_incr_2_extend <= up_wdata[15:0];
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end
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end
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end
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end
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@ -350,7 +381,7 @@ module up_dac_channel #(
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up_rack_int <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr[3:0])
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4'h0: up_rdata_int <= { 16'd0, up_dac_dds_scale_1};
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4'h0: up_rdata_int <= { 10'd0, dds_phase_w, up_dac_dds_scale_1};
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4'h1: up_rdata_int <= { up_dac_dds_init_1, up_dac_dds_incr_1};
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4'h2: up_rdata_int <= { 16'd0, up_dac_dds_scale_2};
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4'h3: up_rdata_int <= { up_dac_dds_init_2, up_dac_dds_incr_2};
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@ -363,6 +394,8 @@ module up_dac_channel #(
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dac_usr_datatype_bits};
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4'h9: up_rdata_int <= { dac_usr_interpolation_m, dac_usr_interpolation_n};
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4'ha: up_rdata_int <= { 30'd0, up_dac_iq_mode};
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4'hb: up_rdata_int <= { up_dac_dds_init_1_extend, up_dac_dds_incr_1_extend};
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4'hc: up_rdata_int <= { up_dac_dds_init_2_extend, up_dac_dds_incr_2_extend};
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default: up_rdata_int <= 0;
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endcase
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end else begin
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@ -404,7 +437,7 @@ module up_dac_channel #(
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// dac control & status
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up_xfer_cntrl #(
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.DATA_WIDTH(177)
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.DATA_WIDTH(240)
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) i_xfer_cntrl (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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@ -418,6 +451,10 @@ module up_dac_channel #(
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up_dac_dds_scale_tc_2,
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up_dac_dds_init_2,
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up_dac_dds_incr_2,
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up_dac_dds_init_1_extend,
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up_dac_dds_incr_1_extend,
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up_dac_dds_init_2_extend,
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up_dac_dds_incr_2_extend,
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up_dac_pat_data_1,
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up_dac_pat_data_2,
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up_dac_data_sel_m,
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@ -431,15 +468,34 @@ module up_dac_channel #(
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dac_iqcor_coeff_1,
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dac_iqcor_coeff_2,
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dac_dds_scale_1,
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dac_dds_init_1,
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dac_dds_incr_1,
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dac_dds_init_1_s,
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dac_dds_incr_1_s,
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dac_dds_scale_2,
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dac_dds_init_2,
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dac_dds_incr_2,
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dac_dds_init_2_s,
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dac_dds_incr_2_s,
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dac_dds_init_1_extend,
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dac_dds_incr_1_extend,
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dac_dds_init_2_extend,
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dac_dds_incr_2_extend,
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dac_pat_data_1,
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dac_pat_data_2,
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dac_data_sel,
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dac_mask_enable,
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dac_src_chan_sel}));
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generate
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if (DDS_PHASE_DW > 16) begin
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localparam DDS_EXT_DW = DDS_PHASE_DW - 16 - 1;
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assign dac_dds_init_1 = {dac_dds_init_1_extend[DDS_EXT_DW:0], dac_dds_init_1_s};
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assign dac_dds_incr_1 = {dac_dds_incr_1_extend[DDS_EXT_DW:0], dac_dds_incr_1_s};
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assign dac_dds_init_2 = {dac_dds_init_2_extend[DDS_EXT_DW:0], dac_dds_init_2_s};
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assign dac_dds_incr_2 = {dac_dds_incr_2_extend[DDS_EXT_DW:0], dac_dds_incr_2_s};
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end else begin
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assign dac_dds_init_1 = dac_dds_init_1_s[DDS_PHASE_DW-1:0];
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assign dac_dds_incr_1 = dac_dds_incr_1_s[DDS_PHASE_DW-1:0];
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assign dac_dds_init_2 = dac_dds_init_2_s[DDS_PHASE_DW-1:0];
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assign dac_dds_incr_2 = dac_dds_incr_2_s[DDS_PHASE_DW-1:0];
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end
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endgenerate
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endmodule
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@ -118,7 +118,7 @@ module up_dac_common #(
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// parameters
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localparam VERSION = 32'h00090162;
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localparam VERSION = 32'h00090262;
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// internal registers
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