ad9081_fmca_ebz/common/versal_transceiver: Separate lane rates for Tx and Rx
parent
3379dd3bdb
commit
78333b2c90
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@ -3,12 +3,14 @@
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proc create_versal_phy {
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proc create_versal_phy {
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{ip_name versal_phy}
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{ip_name versal_phy}
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{num_lanes 2}
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{num_lanes 2}
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{lane_rate 11.88}
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{rx_lane_rate 11.88}
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{tx_lane_rate 11.88}
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{ref_clock 360}
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{ref_clock 360}
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} {
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} {
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set num_quads [expr round(1.0*$num_lanes/4)]
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set num_quads [expr round(1.0*$num_lanes/4)]
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set progdiv_clock [format %.3f [expr $lane_rate * 1000 / 66]]
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set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000 / 66]]
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set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000 / 66]]
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create_bd_cell -type hier ${ip_name}
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create_bd_cell -type hier ${ip_name}
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@ -33,7 +35,7 @@ set_property -dict [list \
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INTERNAL_PRESET JESD204_64B66B \
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INTERNAL_PRESET JESD204_64B66B \
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GT_TYPE GTY \
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GT_TYPE GTY \
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GT_DIRECTION DUPLEX \
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GT_DIRECTION DUPLEX \
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TX_LINE_RATE $lane_rate \
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TX_LINE_RATE $tx_lane_rate \
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TX_PLL_TYPE LCPLL \
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TX_PLL_TYPE LCPLL \
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TX_REFCLK_FREQUENCY $ref_clock \
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TX_REFCLK_FREQUENCY $ref_clock \
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TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \
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TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \
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@ -49,13 +51,13 @@ set_property -dict [list \
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TX_OUTCLK_SOURCE TXPROGDIVCLK \
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TX_OUTCLK_SOURCE TXPROGDIVCLK \
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TXPROGDIV_FREQ_ENABLE true \
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TXPROGDIV_FREQ_ENABLE true \
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TXPROGDIV_FREQ_SOURCE LCPLL \
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TXPROGDIV_FREQ_SOURCE LCPLL \
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TXPROGDIV_FREQ_VAL $progdiv_clock \
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TXPROGDIV_FREQ_VAL $tx_progdiv_clock \
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TX_DIFF_SWING_EMPH_MODE CUSTOM \
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TX_DIFF_SWING_EMPH_MODE CUSTOM \
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TX_64B66B_SCRAMBLER false \
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TX_64B66B_SCRAMBLER false \
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TX_64B66B_ENCODER false \
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TX_64B66B_ENCODER false \
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TX_64B66B_CRC false \
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TX_64B66B_CRC false \
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TX_RATE_GROUP A \
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TX_RATE_GROUP A \
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RX_LINE_RATE $lane_rate \
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RX_LINE_RATE $rx_lane_rate \
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RX_PLL_TYPE LCPLL \
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RX_PLL_TYPE LCPLL \
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RX_REFCLK_FREQUENCY $ref_clock \
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RX_REFCLK_FREQUENCY $ref_clock \
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RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \
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RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \
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@ -69,7 +71,7 @@ set_property -dict [list \
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RX_OUTCLK_SOURCE RXPROGDIVCLK \
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RX_OUTCLK_SOURCE RXPROGDIVCLK \
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RXPROGDIV_FREQ_ENABLE true \
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RXPROGDIV_FREQ_ENABLE true \
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RXPROGDIV_FREQ_SOURCE LCPLL \
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RXPROGDIV_FREQ_SOURCE LCPLL \
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RXPROGDIV_FREQ_VAL $progdiv_clock \
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RXPROGDIV_FREQ_VAL $rx_progdiv_clock \
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INS_LOSS_NYQ 12 \
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INS_LOSS_NYQ 12 \
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RX_EQ_MODE LPM \
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RX_EQ_MODE LPM \
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RX_COUPLING AC \
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RX_COUPLING AC \
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