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ad9625- add an option to control cs monitoring

main
Rejeesh Kutty 2017-05-10 14:22:16 -04:00
parent d374f5b091
commit 78435ebbb7
4 changed files with 104 additions and 100 deletions
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61
library/axi_ad9625/axi_ad9625.v
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@ -47,7 +47,7 @@ module axi_ad9625 #(
// rx_clk is (line-rate/40)
input rx_clk,
input [ 3:0] rx_sof,
input [ 3:0] rx_sof,
input rx_valid,
input [255:0] rx_data,
output rx_ready,
@ -62,8 +62,8 @@ module axi_ad9625 #(
input adc_dovf,
input adc_dunf,
output [ 15:0] adc_sref,
input [ 3:0] adc_raddr_in,
output [ 3:0] adc_raddr_out,
input [ 3:0] adc_raddr_in,
output [ 3:0] adc_raddr_out,
// axi interface
@ -74,49 +74,46 @@ module axi_ad9625 #(
output s_axi_awready,
input s_axi_wvalid,
input [ 31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [ 31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [ 1:0] s_axi_rresp,
output [ 31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
// internal registers
reg [ 31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal clocks & resets
wire up_rstn;
wire up_clk;
reg [ 31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal signals
wire [191:0] adc_data_s;
wire adc_or_s;
wire adc_status_s;
wire up_adc_pn_err_s;
wire up_adc_pn_oos_s;
wire up_adc_or_s;
wire [ 31:0] up_rdata_s[0:1];
wire up_rack_s[0:1];
wire up_wack_s[0:1];
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
wire up_rstn;
wire up_clk;
wire [191:0] adc_data_s;
wire adc_or_s;
wire adc_status_s;
wire adc_sref_sync_s;
wire up_adc_pn_err_s;
wire up_adc_pn_oos_s;
wire up_adc_or_s;
wire [ 31:0] up_rdata_s[0:1];
wire up_rack_s[0:1];
wire up_wack_s[0:1];
wire up_wreq_s;
wire [ 13:0] up_waddr_s;
wire [ 31:0] up_wdata_s;
wire up_rreq_s;
wire [ 13:0] up_raddr_s;
// signal name changes
@ -158,6 +155,7 @@ module axi_ad9625 #(
.adc_or (adc_or_s),
.adc_status (adc_status_s),
.adc_sref (adc_sref),
.adc_sref_sync (adc_sref_sync_s),
.adc_raddr_in (adc_raddr_in),
.adc_raddr_out (adc_raddr_out));
@ -200,6 +198,7 @@ module axi_ad9625 #(
.adc_clk_ratio (32'd16),
.adc_start_code (),
.adc_sync (),
.adc_sref_sync (adc_sref_sync_s),
.up_status_pn_err (up_adc_pn_err_s),
.up_status_pn_oos (up_adc_pn_oos_s),
.up_status_or (up_adc_or_s),

23
library/axi_ad9625/axi_ad9625_channel.v
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@ -34,9 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
@ -62,22 +59,22 @@ module axi_ad9625_channel (
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
input [ 13:0] up_waddr,
input [ 31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
input [ 13:0] up_raddr,
output [ 31:0] up_rdata,
output up_rack);
// internal signals
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire adc_dfmt_enable_s;
wire adc_dfmt_type_s;
wire adc_dfmt_se_s;
wire [ 3:0] adc_pnseq_sel_s;
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire adc_dfmt_enable_s;
wire adc_dfmt_type_s;
wire adc_dfmt_se_s;
wire [ 3:0] adc_pnseq_sel_s;
// instantiations

109
library/axi_ad9625/axi_ad9625_if.v
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@ -46,59 +46,63 @@ module axi_ad9625_if #(
// rx_clk is (line-rate/40)
input rx_clk,
input [ 3:0] rx_sof,
input [ 3:0] rx_sof,
input [255:0] rx_data,
// adc data output
output adc_clk,
input adc_rst,
output reg [191:0] adc_data,
output [191:0] adc_data,
output adc_or,
output reg adc_status,
output reg [ 15:0] adc_sref,
input [ 3:0] adc_raddr_in,
output reg [ 3:0] adc_raddr_out);
output adc_status,
output [ 15:0] adc_sref,
input adc_sref_sync,
input [ 3:0] adc_raddr_in,
output [ 3:0] adc_raddr_out);
// internal registers
reg [191:0] adc_data_cur = 'd0;
reg [191:0] adc_data_prv = 'd0;
reg [ 3:0] adc_waddr = 'd0;
reg [191:0] adc_wdata = 'd0;
reg [191:0] adc_data_int = 'd0;
reg adc_status_int = 'd0;
reg [ 15:0] adc_sref_int = 'd0;
reg [191:0] adc_data_cur = 'd0;
reg [191:0] adc_data_prv = 'd0;
reg [ 3:0] adc_waddr = 'd0;
reg [191:0] adc_wdata = 'd0;
reg [ 3:0] adc_raddr = 'd0;
// internal signals
wire [191:0] adc_rdata_s;
wire [ 3:0] adc_raddr_s;
wire [ 15:0] adc_sref_s;
wire [191:0] adc_data_s;
wire [ 15:0] adc_data_s15_s;
wire [ 15:0] adc_data_s14_s;
wire [ 15:0] adc_data_s13_s;
wire [ 15:0] adc_data_s12_s;
wire [ 15:0] adc_data_s11_s;
wire [ 15:0] adc_data_s10_s;
wire [ 15:0] adc_data_s09_s;
wire [ 15:0] adc_data_s08_s;
wire [ 15:0] adc_data_s07_s;
wire [ 15:0] adc_data_s06_s;
wire [ 15:0] adc_data_s05_s;
wire [ 15:0] adc_data_s04_s;
wire [ 15:0] adc_data_s03_s;
wire [ 15:0] adc_data_s02_s;
wire [ 15:0] adc_data_s01_s;
wire [ 15:0] adc_data_s00_s;
wire [ 31:0] rx_data0_s;
wire [ 31:0] rx_data1_s;
wire [ 31:0] rx_data2_s;
wire [ 31:0] rx_data3_s;
wire [ 31:0] rx_data4_s;
wire [ 31:0] rx_data5_s;
wire [ 31:0] rx_data6_s;
wire [ 31:0] rx_data7_s;
wire [255:0] rx_data_s;
wire [191:0] adc_rdata_s;
wire [ 3:0] adc_raddr_s;
wire [ 15:0] adc_sref_s;
wire [191:0] adc_data_s;
wire [ 15:0] adc_data_s15_s;
wire [ 15:0] adc_data_s14_s;
wire [ 15:0] adc_data_s13_s;
wire [ 15:0] adc_data_s12_s;
wire [ 15:0] adc_data_s11_s;
wire [ 15:0] adc_data_s10_s;
wire [ 15:0] adc_data_s09_s;
wire [ 15:0] adc_data_s08_s;
wire [ 15:0] adc_data_s07_s;
wire [ 15:0] adc_data_s06_s;
wire [ 15:0] adc_data_s05_s;
wire [ 15:0] adc_data_s04_s;
wire [ 15:0] adc_data_s03_s;
wire [ 15:0] adc_data_s02_s;
wire [ 15:0] adc_data_s01_s;
wire [ 15:0] adc_data_s00_s;
wire [ 31:0] rx_data0_s;
wire [ 31:0] rx_data1_s;
wire [ 31:0] rx_data2_s;
wire [ 31:0] rx_data3_s;
wire [ 31:0] rx_data4_s;
wire [ 31:0] rx_data5_s;
wire [ 31:0] rx_data6_s;
wire [ 31:0] rx_data7_s;
wire [255:0] rx_data_s;
// nothing much to do on clock & over-range
@ -107,23 +111,31 @@ module axi_ad9625_if #(
// synchronization mode, multiple instances
assign adc_raddr_s = (ID == 0) ? adc_raddr_out : adc_raddr_in;
assign adc_data = adc_data_int;
assign adc_status = adc_status_int;
assign adc_sref = adc_sref_int;
assign adc_raddr_out = adc_raddr;
assign adc_raddr_s = (ID == 0) ? adc_raddr : adc_raddr_in;
always @(posedge rx_clk) begin
adc_data <= adc_rdata_s;
if (adc_sref_sync == 1'b1) begin
adc_data_int <= adc_rdata_s;
end else begin
adc_data_int <= adc_data_s;
end
if (adc_sref_s != 16'd0) begin
adc_sref <= adc_sref_s;
adc_sref_int <= adc_sref_s;
end
adc_data_cur <= adc_data_s;
adc_data_prv <= adc_data_cur;
if (adc_sref_s == 16'd0) begin
adc_waddr <= adc_waddr + 1'b1;
adc_raddr_out <= adc_raddr_out + 1'b1;
adc_raddr <= adc_raddr + 1'b1;
end else begin
adc_waddr <= 4'h0;
adc_raddr_out <= 4'h8;
adc_raddr <= 4'h8;
end
case (adc_sref)
case (adc_sref_int)
16'h8000: adc_wdata <= {adc_data_cur[179:0], adc_data_prv[191:180]};
16'h4000: adc_wdata <= {adc_data_cur[167:0], adc_data_prv[191:168]};
16'h2000: adc_wdata <= {adc_data_cur[155:0], adc_data_prv[191:156]};
@ -191,9 +203,9 @@ module axi_ad9625_if #(
always @(posedge rx_clk) begin
if (adc_rst == 1'b1) begin
adc_status <= 1'b0;
adc_status_int <= 1'b0;
end else begin
adc_status <= 1'b1;
adc_status_int <= 1'b1;
end
end
@ -211,7 +223,6 @@ module axi_ad9625_if #(
// frame-alignment
genvar n;
generate
for (n = 0; n < 8; n = n + 1) begin: g_xcvr_if
ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if (

11
library/axi_ad9625/axi_ad9625_pnmon.v
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@ -34,9 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
@ -54,16 +51,16 @@ module axi_ad9625_pnmon (
// processor interface PN9 (0x0), PN23 (0x1)
input [ 3:0] adc_pnseq_sel);
input [ 3:0] adc_pnseq_sel);
// internal registers
reg [191:0] adc_pn_data_in = 'd0;
reg [191:0] adc_pn_data_pn = 'd0;
reg [191:0] adc_pn_data_in = 'd0;
reg [191:0] adc_pn_data_pn = 'd0;
// internal signals
wire [191:0] adc_pn_data_pn_s;
wire [191:0] adc_pn_data_pn_s;
// PN23 function