ad9625- add an option to control cs monitoring

library/axi_ad9625/axi_ad9625.v

@@ -89,23 +89,20 @@ module axi_ad9625 #(
   input       [  2:0]     s_axi_awprot,
   input       [  2:0]     s_axi_arprot);
 
-
   // internal registers
 
   reg         [ 31:0]     up_rdata = 'd0;
   reg                     up_rack = 'd0;
   reg                     up_wack = 'd0;
 
-  // internal clocks & resets
+  // internal signals
 
   wire                    up_rstn;
   wire                    up_clk;
-
-  // internal signals
-
   wire        [191:0]     adc_data_s;
   wire                    adc_or_s;
   wire                    adc_status_s;
+  wire                    adc_sref_sync_s;
   wire                    up_adc_pn_err_s;
   wire                    up_adc_pn_oos_s;
   wire                    up_adc_or_s;
@@ -158,6 +155,7 @@ module axi_ad9625 #(
     .adc_or (adc_or_s),
     .adc_status (adc_status_s),
     .adc_sref (adc_sref),
+    .adc_sref_sync (adc_sref_sync_s),
     .adc_raddr_in (adc_raddr_in),
     .adc_raddr_out (adc_raddr_out));
 
@@ -200,6 +198,7 @@ module axi_ad9625 #(
     .adc_clk_ratio (32'd16),
     .adc_start_code (),
     .adc_sync (),
+    .adc_sref_sync (adc_sref_sync_s),
     .up_status_pn_err (up_adc_pn_err_s),
     .up_status_pn_oos (up_adc_pn_oos_s),
     .up_status_or (up_adc_or_s),

library/axi_ad9625/axi_ad9625_channel.v

@@ -34,9 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ADC channel-
 
 `timescale 1ns/100ps
 
@@ -62,12 +59,12 @@ module axi_ad9625_channel (
   input                   up_rstn,
   input                   up_clk,
   input                   up_wreq,
-  input       [13:0]      up_waddr,
+  input       [ 13:0]     up_waddr,
-  input       [31:0]      up_wdata,
+  input       [ 31:0]     up_wdata,
   output                  up_wack,
   input                   up_rreq,
-  input       [13:0]      up_raddr,
+  input       [ 13:0]     up_raddr,
-  output      [31:0]      up_rdata,
+  output      [ 31:0]     up_rdata,
   output                  up_rack);
 
   // internal signals

library/axi_ad9625/axi_ad9625_if.v

@@ -53,20 +53,24 @@ module axi_ad9625_if #(
 
   output                  adc_clk,
   input                   adc_rst,
-  output  reg [191:0]     adc_data,
+  output      [191:0]     adc_data,
   output                  adc_or,
-  output  reg             adc_status,
+  output                  adc_status,
-  output  reg [ 15:0]     adc_sref,
+  output      [ 15:0]     adc_sref,
+  input                   adc_sref_sync,
   input       [  3:0]     adc_raddr_in,
-  output  reg [ 3:0]      adc_raddr_out);
+  output      [  3:0]     adc_raddr_out);
-
 
   // internal registers
 
+  reg         [191:0]     adc_data_int = 'd0;
+  reg                     adc_status_int = 'd0;
+  reg         [ 15:0]     adc_sref_int = 'd0;
   reg         [191:0]     adc_data_cur = 'd0;
   reg         [191:0]     adc_data_prv = 'd0;
   reg         [  3:0]     adc_waddr = 'd0;
   reg         [191:0]     adc_wdata = 'd0;
+  reg         [  3:0]     adc_raddr = 'd0;
 
   // internal signals
 
@@ -107,23 +111,31 @@ module axi_ad9625_if #(
 
   // synchronization mode, multiple instances
 
-  assign adc_raddr_s = (ID == 0) ? adc_raddr_out : adc_raddr_in;
+  assign adc_data = adc_data_int;
+  assign adc_status = adc_status_int;
+  assign adc_sref = adc_sref_int;
+  assign adc_raddr_out = adc_raddr;
+  assign adc_raddr_s = (ID == 0) ? adc_raddr : adc_raddr_in;
 
   always @(posedge rx_clk) begin
-    adc_data <= adc_rdata_s;
+    if (adc_sref_sync == 1'b1) begin
+      adc_data_int <= adc_rdata_s;
+    end else begin
+      adc_data_int <= adc_data_s;
+    end
     if (adc_sref_s != 16'd0) begin
-      adc_sref <= adc_sref_s;
+      adc_sref_int <= adc_sref_s;
     end
     adc_data_cur <= adc_data_s;
     adc_data_prv <= adc_data_cur;
     if (adc_sref_s == 16'd0) begin
       adc_waddr <= adc_waddr + 1'b1;
-      adc_raddr_out <= adc_raddr_out + 1'b1;
+      adc_raddr <= adc_raddr + 1'b1;
     end else begin
       adc_waddr <= 4'h0;
-      adc_raddr_out <= 4'h8;
+      adc_raddr <= 4'h8;
     end
-    case (adc_sref)
+    case (adc_sref_int)
       16'h8000: adc_wdata <= {adc_data_cur[179:0], adc_data_prv[191:180]};
       16'h4000: adc_wdata <= {adc_data_cur[167:0], adc_data_prv[191:168]};
       16'h2000: adc_wdata <= {adc_data_cur[155:0], adc_data_prv[191:156]};
@@ -191,9 +203,9 @@ module axi_ad9625_if #(
 
   always @(posedge rx_clk) begin
     if (adc_rst == 1'b1) begin
-      adc_status <= 1'b0;
+      adc_status_int <= 1'b0;
     end else begin
-      adc_status <= 1'b1;
+      adc_status_int <= 1'b1;
     end
   end
 
@@ -211,7 +223,6 @@ module axi_ad9625_if #(
   // frame-alignment
 
   genvar n;
-
   generate
   for (n = 0; n < 8; n = n + 1) begin: g_xcvr_if
   ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if (

library/axi_ad9625/axi_ad9625_pnmon.v

@@ -34,9 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// PN monitors
 
 `timescale 1ns/100ps