ad9625- add an option to control cs monitoring
Rejeesh Kutty
parent
d374f5b091
commit
78435ebbb7
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@ -89,23 +89,20 @@ module axi_ad9625 #(
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input [ 2:0] s_axi_awprot,
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input [ 2:0] s_axi_arprot);
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// internal registers
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reg [ 31:0] up_rdata = 'd0;
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reg up_rack = 'd0;
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reg up_wack = 'd0;
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// internal clocks & resets
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// internal signals
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wire up_rstn;
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wire up_clk;
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// internal signals
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wire [191:0] adc_data_s;
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wire adc_or_s;
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wire adc_status_s;
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wire adc_sref_sync_s;
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wire up_adc_pn_err_s;
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wire up_adc_pn_oos_s;
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wire up_adc_or_s;
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@ -158,6 +155,7 @@ module axi_ad9625 #(
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.adc_or (adc_or_s),
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.adc_status (adc_status_s),
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.adc_sref (adc_sref),
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.adc_sref_sync (adc_sref_sync_s),
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.adc_raddr_in (adc_raddr_in),
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.adc_raddr_out (adc_raddr_out));
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@ -200,6 +198,7 @@ module axi_ad9625 #(
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.adc_clk_ratio (32'd16),
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.adc_start_code (),
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.adc_sync (),
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.adc_sref_sync (adc_sref_sync_s),
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.up_status_pn_err (up_adc_pn_err_s),
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.up_status_pn_oos (up_adc_pn_oos_s),
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.up_status_or (up_adc_or_s),
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@ -34,9 +34,6 @@
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ADC channel-
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`timescale 1ns/100ps
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@ -53,20 +53,24 @@ module axi_ad9625_if #(
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output adc_clk,
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input adc_rst,
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output reg [191:0] adc_data,
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output [191:0] adc_data,
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output adc_or,
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output reg adc_status,
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output reg [ 15:0] adc_sref,
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output adc_status,
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output [ 15:0] adc_sref,
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input adc_sref_sync,
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input [ 3:0] adc_raddr_in,
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output reg [ 3:0] adc_raddr_out);
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output [ 3:0] adc_raddr_out);
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// internal registers
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reg [191:0] adc_data_int = 'd0;
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reg adc_status_int = 'd0;
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reg [ 15:0] adc_sref_int = 'd0;
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reg [191:0] adc_data_cur = 'd0;
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reg [191:0] adc_data_prv = 'd0;
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reg [ 3:0] adc_waddr = 'd0;
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reg [191:0] adc_wdata = 'd0;
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reg [ 3:0] adc_raddr = 'd0;
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// internal signals
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@ -107,23 +111,31 @@ module axi_ad9625_if #(
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// synchronization mode, multiple instances
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assign adc_raddr_s = (ID == 0) ? adc_raddr_out : adc_raddr_in;
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assign adc_data = adc_data_int;
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assign adc_status = adc_status_int;
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assign adc_sref = adc_sref_int;
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assign adc_raddr_out = adc_raddr;
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assign adc_raddr_s = (ID == 0) ? adc_raddr : adc_raddr_in;
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always @(posedge rx_clk) begin
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adc_data <= adc_rdata_s;
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if (adc_sref_sync == 1'b1) begin
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adc_data_int <= adc_rdata_s;
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end else begin
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adc_data_int <= adc_data_s;
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end
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if (adc_sref_s != 16'd0) begin
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adc_sref <= adc_sref_s;
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adc_sref_int <= adc_sref_s;
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end
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adc_data_cur <= adc_data_s;
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adc_data_prv <= adc_data_cur;
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if (adc_sref_s == 16'd0) begin
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adc_waddr <= adc_waddr + 1'b1;
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adc_raddr_out <= adc_raddr_out + 1'b1;
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adc_raddr <= adc_raddr + 1'b1;
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end else begin
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adc_waddr <= 4'h0;
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adc_raddr_out <= 4'h8;
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adc_raddr <= 4'h8;
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end
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case (adc_sref)
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case (adc_sref_int)
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16'h8000: adc_wdata <= {adc_data_cur[179:0], adc_data_prv[191:180]};
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16'h4000: adc_wdata <= {adc_data_cur[167:0], adc_data_prv[191:168]};
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16'h2000: adc_wdata <= {adc_data_cur[155:0], adc_data_prv[191:156]};
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@ -191,9 +203,9 @@ module axi_ad9625_if #(
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always @(posedge rx_clk) begin
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if (adc_rst == 1'b1) begin
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adc_status <= 1'b0;
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adc_status_int <= 1'b0;
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end else begin
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adc_status <= 1'b1;
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adc_status_int <= 1'b1;
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end
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end
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@ -211,7 +223,6 @@ module axi_ad9625_if #(
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// frame-alignment
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genvar n;
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generate
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for (n = 0; n < 8; n = n + 1) begin: g_xcvr_if
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ad_xcvr_rx_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_xcvr_if (
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@ -34,9 +34,6 @@
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// PN monitors
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`timescale 1ns/100ps
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