ad9361- vivado synthesis warnings fix
parent
df37a23a48
commit
78f7384150
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@ -34,9 +34,6 @@
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ADC channel-need to work on dual mode for pn sequence
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`timescale 1ns/100ps
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`timescale 1ns/100ps
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@ -34,8 +34,6 @@
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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`timescale 1ns/100ps
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@ -389,6 +387,7 @@ module axi_ad9361_tx_channel (
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.dac_pat_data_1 (dac_pat_data_1_s),
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.dac_pat_data_1 (dac_pat_data_1_s),
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.dac_pat_data_2 (dac_pat_data_2_s),
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.dac_pat_data_2 (dac_pat_data_2_s),
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.dac_data_sel (dac_data_sel_s),
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.dac_data_sel (dac_data_sel_s),
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.dac_iq_mode (),
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.dac_iqcor_enb (dac_iqcor_enb_s),
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.dac_iqcor_enb (dac_iqcor_enb_s),
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.dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s),
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.dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s),
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.dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s),
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.dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s),
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@ -163,6 +163,7 @@ module up_adc_common (
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reg [31:0] up_scratch = 'd0;
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reg [31:0] up_scratch = 'd0;
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reg up_mmcm_resetn = 'd0;
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reg up_mmcm_resetn = 'd0;
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reg up_resetn = 'd0;
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reg up_resetn = 'd0;
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reg up_adc_sync = 'd0;
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reg up_adc_r1_mode = 'd0;
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reg up_adc_r1_mode = 'd0;
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reg up_adc_ddr_edgesel = 'd0;
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reg up_adc_ddr_edgesel = 'd0;
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reg up_adc_pin_mode = 'd0;
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reg up_adc_pin_mode = 'd0;
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@ -176,9 +177,8 @@ module up_adc_common (
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reg up_status_ovf = 'd0;
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reg up_status_ovf = 'd0;
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reg up_status_unf = 'd0;
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reg up_status_unf = 'd0;
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reg [ 7:0] up_usr_chanmax = 'd0;
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reg [ 7:0] up_usr_chanmax = 'd0;
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reg [31:0] up_adc_gpio_out = 'd0;
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reg [31:0] up_adc_start_code = 'd0;
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reg [31:0] up_adc_start_code = 'd0;
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reg up_adc_sync = 'd0;
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reg [31:0] up_adc_gpio_out = 'd0;
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reg up_rack = 'd0;
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reg up_rack = 'd0;
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reg [31:0] up_rdata = 'd0;
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reg [31:0] up_rdata = 'd0;
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@ -190,7 +190,7 @@ module up_adc_common (
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wire up_sync_status_s;
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wire up_sync_status_s;
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wire up_status_ovf_s;
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wire up_status_ovf_s;
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wire up_status_unf_s;
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wire up_status_unf_s;
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wire up_cntrl_xfer_done;
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wire up_cntrl_xfer_done_s;
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wire [31:0] up_adc_clk_count_s;
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wire [31:0] up_adc_clk_count_s;
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// decode block select
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// decode block select
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@ -208,6 +208,7 @@ module up_adc_common (
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up_scratch <= 'd0;
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up_scratch <= 'd0;
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up_mmcm_resetn <= 'd0;
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up_mmcm_resetn <= 'd0;
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up_resetn <= 'd0;
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up_resetn <= 'd0;
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up_adc_sync <= 'd0;
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up_adc_r1_mode <= 'd0;
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up_adc_r1_mode <= 'd0;
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up_adc_ddr_edgesel <= 'd0;
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up_adc_ddr_edgesel <= 'd0;
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up_adc_pin_mode <= 'd0;
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up_adc_pin_mode <= 'd0;
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@ -221,8 +222,8 @@ module up_adc_common (
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up_status_ovf <= 'd0;
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up_status_ovf <= 'd0;
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up_status_unf <= 'd0;
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up_status_unf <= 'd0;
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up_usr_chanmax <= 'd0;
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up_usr_chanmax <= 'd0;
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up_adc_gpio_out <= 'd0;
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up_adc_start_code <= 'd0;
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up_adc_start_code <= 'd0;
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up_adc_gpio_out <= 'd0;
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end else begin
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end else begin
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up_core_preset <= ~up_resetn;
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up_core_preset <= ~up_resetn;
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up_mmcm_preset <= ~up_mmcm_resetn;
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up_mmcm_preset <= ~up_mmcm_resetn;
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@ -235,7 +236,7 @@ module up_adc_common (
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up_resetn <= up_wdata[0];
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up_resetn <= up_wdata[0];
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end
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end
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if (up_adc_sync == 1'b1) begin
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if (up_adc_sync == 1'b1) begin
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if (up_cntrl_xfer_done == 1'b1) begin
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if (up_cntrl_xfer_done_s == 1'b1) begin
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up_adc_sync <= 1'b0;
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up_adc_sync <= 1'b0;
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end
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end
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end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
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end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
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@ -342,7 +343,7 @@ module up_adc_common (
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up_adc_r1_mode,
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up_adc_r1_mode,
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up_adc_ddr_edgesel,
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up_adc_ddr_edgesel,
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up_adc_pin_mode}),
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up_adc_pin_mode}),
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.up_xfer_done (up_cntrl_xfer_done),
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.up_xfer_done (up_cntrl_xfer_done_s),
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.d_rst (adc_rst),
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.d_rst (adc_rst),
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.d_clk (adc_clk),
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.d_clk (adc_clk),
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.d_data_cntrl ({ adc_sync,
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.d_data_cntrl ({ adc_sync,
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@ -115,6 +115,8 @@ module up_delay_cntrl (
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wire [(DATA_WIDTH-1):0] up_drdata2_s;
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wire [(DATA_WIDTH-1):0] up_drdata2_s;
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wire [(DATA_WIDTH-1):0] up_drdata1_s;
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wire [(DATA_WIDTH-1):0] up_drdata1_s;
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wire [(DATA_WIDTH-1):0] up_drdata0_s;
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wire [(DATA_WIDTH-1):0] up_drdata0_s;
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wire [(DATA_WIDTH-1):0] up_dld_s;
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wire [((DATA_WIDTH*5)-1):0] up_dwdata_s;
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// variables
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// variables
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@ -172,23 +174,24 @@ module up_delay_cntrl (
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generate
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generate
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for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dwr
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for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dwr
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always @(negedge up_rstn or posedge up_clk) begin
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assign up_dld_s[n] = (up_waddr[7:0] == n) ? up_wreq_s : 1'b0;
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if (up_rstn == 0) begin
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assign up_dwdata_s[((n*5)+4):(n*5)] = (up_waddr[7:0] == n) ?
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up_dld[n] <= 'd0;
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up_wdata[4:0] : up_dwdata[((n*5)+4):(n*5)];
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up_dwdata[((n*5)+4):(n*5)] <= 'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == n)) begin
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up_dld[n] <= 1'd1;
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up_dwdata[((n*5)+4):(n*5)] <= up_wdata[4:0];
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end else begin
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up_dld[n] <= 1'd0;
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up_dwdata[((n*5)+4):(n*5)] <= up_dwdata[((n*5)+4):(n*5)];
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end
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end
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end
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end
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end
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endgenerate
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endgenerate
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_dld <= 'd0;
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up_dwdata <= 'd0;
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end else begin
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up_dld <= up_dld_s;
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if (up_wreq_s == 1'b1) begin
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up_dwdata <= up_dwdata_s;
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end
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end
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end
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// resets
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// resets
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ad_rst i_delay_rst_reg (
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ad_rst i_delay_rst_reg (
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