ad9361- vivado synthesis warnings fix

library/axi_ad9361/axi_ad9361_rx_channel.v

@@ -34,9 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
-// ADC channel-need to work on dual mode for pn sequence
 
 `timescale 1ns/100ps
 

library/axi_ad9361/axi_ad9361_tx_channel.v

@@ -34,8 +34,6 @@
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
-// ***************************************************************************
-// ***************************************************************************
 
 `timescale 1ns/100ps
 
@@ -389,6 +387,7 @@ module axi_ad9361_tx_channel (
     .dac_pat_data_1 (dac_pat_data_1_s),
     .dac_pat_data_2 (dac_pat_data_2_s),
     .dac_data_sel (dac_data_sel_s),
+    .dac_iq_mode (),
     .dac_iqcor_enb (dac_iqcor_enb_s),
     .dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s),
     .dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s),

library/common/up_adc_common.v

@@ -163,6 +163,7 @@ module up_adc_common (
   reg     [31:0]  up_scratch = 'd0;
   reg             up_mmcm_resetn = 'd0;
   reg             up_resetn = 'd0;
+  reg             up_adc_sync = 'd0;
   reg             up_adc_r1_mode = 'd0;
   reg             up_adc_ddr_edgesel = 'd0;
   reg             up_adc_pin_mode = 'd0;
@@ -176,9 +177,8 @@ module up_adc_common (
   reg             up_status_ovf = 'd0;
   reg             up_status_unf = 'd0;
   reg     [ 7:0]  up_usr_chanmax = 'd0;
-  reg     [31:0]  up_adc_gpio_out = 'd0;
   reg     [31:0]  up_adc_start_code = 'd0;
-  reg             up_adc_sync = 'd0;
+  reg     [31:0]  up_adc_gpio_out = 'd0;
   reg             up_rack = 'd0;
   reg     [31:0]  up_rdata = 'd0;
 
@@ -190,7 +190,7 @@ module up_adc_common (
   wire            up_sync_status_s;
   wire            up_status_ovf_s;
   wire            up_status_unf_s;
-  wire            up_cntrl_xfer_done;
+  wire            up_cntrl_xfer_done_s;
   wire    [31:0]  up_adc_clk_count_s;
 
   // decode block select
@@ -208,6 +208,7 @@ module up_adc_common (
       up_scratch <= 'd0;
       up_mmcm_resetn <= 'd0;
       up_resetn <= 'd0;
+      up_adc_sync <= 'd0;
       up_adc_r1_mode <= 'd0;
       up_adc_ddr_edgesel <= 'd0;
       up_adc_pin_mode <= 'd0;
@@ -221,8 +222,8 @@ module up_adc_common (
       up_status_ovf <= 'd0;
       up_status_unf <= 'd0;
       up_usr_chanmax <= 'd0;
-      up_adc_gpio_out <= 'd0;
       up_adc_start_code <= 'd0;
+      up_adc_gpio_out <= 'd0;
     end else begin
       up_core_preset <= ~up_resetn;
       up_mmcm_preset <= ~up_mmcm_resetn;
@@ -235,7 +236,7 @@ module up_adc_common (
         up_resetn <= up_wdata[0];
       end
       if (up_adc_sync == 1'b1) begin
-        if (up_cntrl_xfer_done == 1'b1) begin
+        if (up_cntrl_xfer_done_s == 1'b1) begin
           up_adc_sync <= 1'b0;
         end
       end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
@@ -342,7 +343,7 @@ module up_adc_common (
                       up_adc_r1_mode,
                       up_adc_ddr_edgesel,
                       up_adc_pin_mode}),
-    .up_xfer_done (up_cntrl_xfer_done),
+    .up_xfer_done (up_cntrl_xfer_done_s),
     .d_rst (adc_rst),
     .d_clk (adc_clk),
     .d_data_cntrl ({  adc_sync,

library/common/up_delay_cntrl.v

@@ -115,6 +115,8 @@ module up_delay_cntrl (
   wire    [(DATA_WIDTH-1):0]      up_drdata2_s;
   wire    [(DATA_WIDTH-1):0]      up_drdata1_s;
   wire    [(DATA_WIDTH-1):0]      up_drdata0_s;
+  wire    [(DATA_WIDTH-1):0]      up_dld_s;
+  wire    [((DATA_WIDTH*5)-1):0]  up_dwdata_s;
 
   // variables
 
@@ -172,22 +174,23 @@ module up_delay_cntrl (
 
   generate
   for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dwr
+  assign up_dld_s[n] = (up_waddr[7:0] == n) ? up_wreq_s : 1'b0;
+  assign up_dwdata_s[((n*5)+4):(n*5)] = (up_waddr[7:0] == n) ?
+    up_wdata[4:0] : up_dwdata[((n*5)+4):(n*5)];
+  end
+  endgenerate
+
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
-      up_dld[n] <= 'd0;
+      up_dld <= 'd0;
-      up_dwdata[((n*5)+4):(n*5)] <= 'd0;
+      up_dwdata <= 'd0;
     end else begin
-      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == n)) begin
+      up_dld <= up_dld_s;
-        up_dld[n] <= 1'd1;
+      if (up_wreq_s == 1'b1) begin
-        up_dwdata[((n*5)+4):(n*5)] <= up_wdata[4:0];
+        up_dwdata <= up_dwdata_s;
-      end else begin
-        up_dld[n] <= 1'd0;
-        up_dwdata[((n*5)+4):(n*5)] <= up_dwdata[((n*5)+4):(n*5)];
       end
     end
   end
-  end
-  endgenerate
 
   // resets