diff --git a/projects/pzsdr/ccbrk/Makefile b/projects/pzsdr/ccbrk/Makefile index 41615cbcf..1ee659550 100644 --- a/projects/pzsdr/ccbrk/Makefile +++ b/projects/pzsdr/ccbrk/Makefile @@ -24,9 +24,8 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr +M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr -M_DEPS += ../../../library/util_gtlb/util_gtlb.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr @@ -61,9 +60,8 @@ clean-all:clean make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_gpreg clean - make -C ../../../library/axi_jesd_gt clean + make -C ../../../library/xilinx/axi_xcvrlb clean make -C ../../../library/util_cpack clean - make -C ../../../library/util_gtlb clean make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_upack clean make -C ../../../library/util_wfifo clean @@ -78,9 +76,8 @@ lib: make -C ../../../library/axi_ad9361 make -C ../../../library/axi_dmac make -C ../../../library/axi_gpreg - make -C ../../../library/axi_jesd_gt + make -C ../../../library/xilinx/axi_xcvrlb make -C ../../../library/util_cpack - make -C ../../../library/util_gtlb make -C ../../../library/util_tdd_sync make -C ../../../library/util_upack make -C ../../../library/util_wfifo diff --git a/projects/pzsdr/ccbrk/system_constr.xdc b/projects/pzsdr/ccbrk/system_constr.xdc index 05083fdc9..ca0b31e54 100644 --- a/projects/pzsdr/ccbrk/system_constr.xdc +++ b/projects/pzsdr/ccbrk/system_constr.xdc @@ -1,6 +1,6 @@ ## constraints -## loopback +## loopback (P2/P13 are pin swapped on board - so skip gp_*[65]) ## p4 set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports gp_out[0]] ; ## IO_L2P_T0_33 @@ -220,39 +220,19 @@ set_property -dict {PACKAGE_PIN AE1} [get_ports gt_tx_n[2]] set_property -dict {PACKAGE_PIN AC2} [get_ports gt_tx_p[3]] ; ## MGTXTXP3_111 set_property -dict {PACKAGE_PIN AC1} [get_ports gt_tx_n[3]] ; ## MGTXTXN3_111 -## clocks - -create_clock -name ref_clk -period 4.00 [get_ports gt_ref_clk_p] -create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] -create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] -create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] -create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] -create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] -create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] -create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] -create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] - -## MIO loopbacks (fixed-io) -## the following are connected to AD9361 GPIO - -## JX4.86 A23 PS_MIO12_500_JX4 <==> JX4.2 NA AD9361_GPO1 -## JX4.88 B26 PS_MIO11_500_JX4 <==> JX4.1 NA AD9361_GPO0 -## JX4.91 B25 PS_MIO13_500_JX4 <==> JX4.3 NA AD9361_GPO2 -## JX4.93 D23 PS_MIO14_500_JX4 <==> JX4.4 NA AD9361_GPO3 - -## the following are mio-to-mio loopback (excluding Push-Buttons to LED) - -## JX4.92 E17 PS_MIO46_501_JX4 <==> JX4.94 B19 PS_MIO47_501_JX4 - -## the following are mio-to-pl loopback - -## JX4.97 E26 PS_MIO00_500_JX4 <==> JX1.76 K3 IO_L11N_T1_SRCC_33 -## JX4.100 B20 PS_MIO51_501_JX4 <==> JX4.67 A9 IO_L17P_T2_34 -## JX4.85 C24 PS_MIO15_500_JX4 <==> JX4.37 E5 IO_L7N_T1_34 -## JX4.87 A25 PS_MIO10_500_JX4 <==> JX4.42 E6 IO_L10P_T1_34 +## mio set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[0]] ; ## IO_L11N_T1_SRCC_33 set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[1]] ; ## IO_L17P_T2_34 set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[2]] ; ## IO_L7N_T1_34 set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[3]] ; ## IO_L10P_T1_34 +## clocks + +create_clock -name ref_clk -period 4.00 [get_ports gt_ref_clk_p] +create_clock -name xcvr_clk_0 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[0].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK] +create_clock -name xcvr_clk_1 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[1].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK] +create_clock -name xcvr_clk_2 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[2].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK] +create_clock -name xcvr_clk_3 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[3].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK] + + diff --git a/projects/pzsdr/ccbrk/system_project.tcl b/projects/pzsdr/ccbrk/system_project.tcl index 1aabab6f4..fe13d542f 100644 --- a/projects/pzsdr/ccbrk/system_project.tcl +++ b/projects/pzsdr/ccbrk/system_project.tcl @@ -1,6 +1,4 @@ - - source ../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl @@ -14,10 +12,7 @@ adi_project_files ccbrk_pzsdr [list \ "$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \ "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ] -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc] -set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc] - +set_property is_enabled false [get_files *axi_gpreg_constr.xdc] adi_project_run ccbrk_pzsdr diff --git a/projects/pzsdr/ccbrk/system_top.v b/projects/pzsdr/ccbrk/system_top.v index 585b2022d..c3d296b81 100644 --- a/projects/pzsdr/ccbrk/system_top.v +++ b/projects/pzsdr/ccbrk/system_top.v @@ -39,147 +39,79 @@ module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - iic_scl, - iic_sda, + inout iic_scl, + inout iic_sda, - gpio_bd, + inout [11:0] gpio_bd, - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, - enable, - txnrx, - clk_out, + output enable, + output txnrx, + input clk_out, - gpio_clksel, - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status, + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, - spi_csn, - spi_clk, - spi_mosi, - spi_miso, + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, - gp_out, - gp_in, - gp_in_mio, - gp_in_1, + output [87:0] gp_out, + input [87:0] gp_in, + input [ 3:0] gp_in_mio, + input gp_in_1, - gt_ref_clk_p, - gt_ref_clk_n, - gt_tx_p, - gt_tx_n, - gt_rx_p, - gt_rx_n); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout iic_scl; - inout iic_sda; - - inout [11:0] gpio_bd; - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - output enable; - output txnrx; - input clk_out; - - inout gpio_clksel; - inout gpio_resetb; - inout gpio_sync; - inout gpio_en_agc; - inout [ 3:0] gpio_ctl; - inout [ 7:0] gpio_status; - - output spi_csn; - output spi_clk; - output spi_mosi; - input spi_miso; - - output [87:0] gp_out; - input [87:0] gp_in; - input [ 3:0] gp_in_mio; - input gp_in_1; - - input gt_ref_clk_p; - input gt_ref_clk_n; - output [ 3:0] gt_tx_p; - output [ 3:0] gt_tx_n; - input [ 3:0] gt_rx_p; - input [ 3:0] gt_rx_n; + input gt_ref_clk_p, + input gt_ref_clk_n, + output [ 3:0] gt_tx_p, + output [ 3:0] gt_tx_n, + input [ 3:0] gt_rx_p, + input [ 3:0] gt_rx_n); // internal signals wire gt_ref_clk; + wire [31:0] gp_misc_s; wire [95:0] gp_out_s; wire [95:0] gp_in_s; wire [63:0] gpio_i; @@ -192,10 +124,15 @@ module system_top ( assign gp_out[42:42] = (gpio_o[61] == 1'b1) ? clk_out : gp_out_s[42:42]; assign gp_out[41: 0] = gp_out_s[41: 0]; - assign gp_in_s[95:93] = 3'd0; - assign gp_in_s[92:92] = gp_in_1; - assign gp_in_s[91:88] = gp_in_mio; - assign gp_in_s[87: 0] = gp_in; + assign gp_in_s[95:88] = gp_out_s[95:88]; + assign gp_in_s[87:66] = gp_in[87:66]; + assign gp_in_s[65:65] = gp_out_s[65]; + assign gp_in_s[64: 0] = gp_in[64:0]; + + assign gp_misc_s[31: 9] = 23'd0; + assign gp_misc_s[ 8: 8] = gp_in_1; + assign gp_misc_s[ 7: 4] = 4'd0; + assign gp_misc_s[ 3: 0] = gp_in_mio; // instantiations @@ -249,29 +186,19 @@ module system_top ( .gp_in_0 (gp_in_s[31:0]), .gp_in_1 (gp_in_s[63:32]), .gp_in_2 (gp_in_s[95:64]), + .gp_in_3 (gp_misc_s), .gp_out_0 (gp_out_s[31:0]), .gp_out_1 (gp_out_s[63:32]), .gp_out_2 (gp_out_s[95:64]), + .gp_out_3 (), .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), .gt_ref_clk (gt_ref_clk), - .gt_rx_0_n (gt_rx_n[0]), - .gt_rx_0_p (gt_rx_p[0]), - .gt_rx_1_n (gt_rx_n[1]), - .gt_rx_1_p (gt_rx_p[1]), - .gt_rx_2_n (gt_rx_n[2]), - .gt_rx_2_p (gt_rx_p[2]), - .gt_rx_3_n (gt_rx_n[3]), - .gt_rx_3_p (gt_rx_p[3]), - .gt_tx_0_n (gt_tx_n[0]), - .gt_tx_0_p (gt_tx_p[0]), - .gt_tx_1_n (gt_tx_n[1]), - .gt_tx_1_p (gt_tx_p[1]), - .gt_tx_2_n (gt_tx_n[2]), - .gt_tx_2_p (gt_tx_p[2]), - .gt_tx_3_n (gt_tx_n[3]), - .gt_tx_3_p (gt_tx_p[3]), + .gt_rx_n (gt_rx_n), + .gt_rx_p (gt_rx_p), + .gt_tx_n (gt_tx_n), + .gt_tx_p (gt_tx_p), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .otg_vbusoc (1'b0),