ccbrk- test updates
Rejeesh Kutty
parent
a2e60cf693
commit
79f34c9de7
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@ -24,9 +24,8 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
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M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
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M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
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M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
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M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr
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M_DEPS += ../../../library/util_cpack/util_cpack.xpr
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M_DEPS += ../../../library/util_gtlb/util_gtlb.xpr
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M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
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M_DEPS += ../../../library/util_upack/util_upack.xpr
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M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
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@ -61,9 +60,8 @@ clean-all:clean
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make -C ../../../library/axi_ad9361 clean
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make -C ../../../library/axi_dmac clean
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make -C ../../../library/axi_gpreg clean
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make -C ../../../library/axi_jesd_gt clean
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make -C ../../../library/xilinx/axi_xcvrlb clean
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make -C ../../../library/util_cpack clean
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make -C ../../../library/util_gtlb clean
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make -C ../../../library/util_tdd_sync clean
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make -C ../../../library/util_upack clean
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make -C ../../../library/util_wfifo clean
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@ -78,9 +76,8 @@ lib:
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make -C ../../../library/axi_ad9361
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make -C ../../../library/axi_dmac
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make -C ../../../library/axi_gpreg
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make -C ../../../library/axi_jesd_gt
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make -C ../../../library/xilinx/axi_xcvrlb
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make -C ../../../library/util_cpack
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make -C ../../../library/util_gtlb
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make -C ../../../library/util_tdd_sync
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make -C ../../../library/util_upack
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make -C ../../../library/util_wfifo
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@ -1,6 +1,6 @@
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## constraints
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## loopback
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## loopback (P2/P13 are pin swapped on board - so skip gp_*[65])
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## p4
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set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports gp_out[0]] ; ## IO_L2P_T0_33
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@ -220,39 +220,19 @@ set_property -dict {PACKAGE_PIN AE1} [get_ports gt_tx_n[2]]
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set_property -dict {PACKAGE_PIN AC2} [get_ports gt_tx_p[3]] ; ## MGTXTXP3_111
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set_property -dict {PACKAGE_PIN AC1} [get_ports gt_tx_n[3]] ; ## MGTXTXN3_111
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## clocks
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create_clock -name ref_clk -period 4.00 [get_ports gt_ref_clk_p]
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create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
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create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
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create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[2].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
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create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
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create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[3].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
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## MIO loopbacks (fixed-io)
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## the following are connected to AD9361 GPIO
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## JX4.86 A23 PS_MIO12_500_JX4 <==> JX4.2 NA AD9361_GPO1
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## JX4.88 B26 PS_MIO11_500_JX4 <==> JX4.1 NA AD9361_GPO0
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## JX4.91 B25 PS_MIO13_500_JX4 <==> JX4.3 NA AD9361_GPO2
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## JX4.93 D23 PS_MIO14_500_JX4 <==> JX4.4 NA AD9361_GPO3
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## the following are mio-to-mio loopback (excluding Push-Buttons to LED)
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## JX4.92 E17 PS_MIO46_501_JX4 <==> JX4.94 B19 PS_MIO47_501_JX4
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## the following are mio-to-pl loopback
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## JX4.97 E26 PS_MIO00_500_JX4 <==> JX1.76 K3 IO_L11N_T1_SRCC_33
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## JX4.100 B20 PS_MIO51_501_JX4 <==> JX4.67 A9 IO_L17P_T2_34
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## JX4.85 C24 PS_MIO15_500_JX4 <==> JX4.37 E5 IO_L7N_T1_34
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## JX4.87 A25 PS_MIO10_500_JX4 <==> JX4.42 E6 IO_L10P_T1_34
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## mio
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set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[0]] ; ## IO_L11N_T1_SRCC_33
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set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[1]] ; ## IO_L17P_T2_34
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set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[2]] ; ## IO_L7N_T1_34
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set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports gp_in_mio[3]] ; ## IO_L10P_T1_34
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## clocks
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create_clock -name ref_clk -period 4.00 [get_ports gt_ref_clk_p]
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create_clock -name xcvr_clk_0 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[0].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
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create_clock -name xcvr_clk_1 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[1].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
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create_clock -name xcvr_clk_2 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[2].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
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create_clock -name xcvr_clk_3 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[3].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
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@ -1,6 +1,4 @@
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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@ -14,10 +12,7 @@ adi_project_files ccbrk_pzsdr [list \
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"$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
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"$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
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set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
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set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc]
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set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
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set_property is_enabled false [get_files *axi_gpreg_constr.xdc]
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adi_project_run ccbrk_pzsdr
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@ -39,147 +39,79 @@
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module system_top (
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ddr_addr,
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ddr_ba,
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ddr_cas_n,
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ddr_ck_n,
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ddr_ck_p,
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ddr_cke,
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ddr_cs_n,
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ddr_dm,
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ddr_dq,
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ddr_dqs_n,
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ddr_dqs_p,
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ddr_odt,
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ddr_ras_n,
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ddr_reset_n,
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ddr_we_n,
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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fixed_io_ddr_vrn,
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fixed_io_ddr_vrp,
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fixed_io_mio,
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fixed_io_ps_clk,
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fixed_io_ps_porb,
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fixed_io_ps_srstb,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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iic_scl,
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iic_sda,
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inout iic_scl,
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inout iic_sda,
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gpio_bd,
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inout [11:0] gpio_bd,
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rx_clk_in_p,
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rx_clk_in_n,
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rx_frame_in_p,
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rx_frame_in_n,
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rx_data_in_p,
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rx_data_in_n,
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tx_clk_out_p,
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tx_clk_out_n,
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tx_frame_out_p,
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tx_frame_out_n,
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tx_data_out_p,
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tx_data_out_n,
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input rx_clk_in_p,
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input rx_clk_in_n,
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input rx_frame_in_p,
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input rx_frame_in_n,
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input [ 5:0] rx_data_in_p,
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input [ 5:0] rx_data_in_n,
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output tx_clk_out_p,
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output tx_clk_out_n,
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output tx_frame_out_p,
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output tx_frame_out_n,
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output [ 5:0] tx_data_out_p,
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output [ 5:0] tx_data_out_n,
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enable,
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txnrx,
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clk_out,
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output enable,
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output txnrx,
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input clk_out,
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gpio_clksel,
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gpio_resetb,
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gpio_sync,
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gpio_en_agc,
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gpio_ctl,
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gpio_status,
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inout gpio_clksel,
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inout gpio_resetb,
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inout gpio_sync,
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inout gpio_en_agc,
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inout [ 3:0] gpio_ctl,
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inout [ 7:0] gpio_status,
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spi_csn,
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spi_clk,
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spi_mosi,
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spi_miso,
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output spi_csn,
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output spi_clk,
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output spi_mosi,
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input spi_miso,
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gp_out,
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gp_in,
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gp_in_mio,
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gp_in_1,
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output [87:0] gp_out,
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input [87:0] gp_in,
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input [ 3:0] gp_in_mio,
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input gp_in_1,
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gt_ref_clk_p,
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gt_ref_clk_n,
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gt_tx_p,
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gt_tx_n,
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gt_rx_p,
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gt_rx_n);
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inout [14:0] ddr_addr;
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inout [ 2:0] ddr_ba;
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inout ddr_cas_n;
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inout ddr_ck_n;
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inout ddr_ck_p;
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inout ddr_cke;
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inout ddr_cs_n;
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inout [ 3:0] ddr_dm;
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inout [31:0] ddr_dq;
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inout [ 3:0] ddr_dqs_n;
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inout [ 3:0] ddr_dqs_p;
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inout ddr_odt;
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inout ddr_ras_n;
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inout ddr_reset_n;
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inout ddr_we_n;
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inout fixed_io_ddr_vrn;
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inout fixed_io_ddr_vrp;
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inout [53:0] fixed_io_mio;
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inout fixed_io_ps_clk;
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inout fixed_io_ps_porb;
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inout fixed_io_ps_srstb;
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inout iic_scl;
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inout iic_sda;
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inout [11:0] gpio_bd;
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input rx_clk_in_p;
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input rx_clk_in_n;
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input rx_frame_in_p;
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input rx_frame_in_n;
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input [ 5:0] rx_data_in_p;
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input [ 5:0] rx_data_in_n;
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output tx_clk_out_p;
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output tx_clk_out_n;
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output tx_frame_out_p;
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output tx_frame_out_n;
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output [ 5:0] tx_data_out_p;
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output [ 5:0] tx_data_out_n;
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output enable;
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output txnrx;
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input clk_out;
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inout gpio_clksel;
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inout gpio_resetb;
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inout gpio_sync;
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inout gpio_en_agc;
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inout [ 3:0] gpio_ctl;
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inout [ 7:0] gpio_status;
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output spi_csn;
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output spi_clk;
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output spi_mosi;
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input spi_miso;
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output [87:0] gp_out;
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input [87:0] gp_in;
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input [ 3:0] gp_in_mio;
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input gp_in_1;
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input gt_ref_clk_p;
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input gt_ref_clk_n;
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output [ 3:0] gt_tx_p;
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output [ 3:0] gt_tx_n;
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input [ 3:0] gt_rx_p;
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input [ 3:0] gt_rx_n;
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input gt_ref_clk_p,
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input gt_ref_clk_n,
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output [ 3:0] gt_tx_p,
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output [ 3:0] gt_tx_n,
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input [ 3:0] gt_rx_p,
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input [ 3:0] gt_rx_n);
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// internal signals
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wire gt_ref_clk;
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wire [31:0] gp_misc_s;
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wire [95:0] gp_out_s;
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wire [95:0] gp_in_s;
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wire [63:0] gpio_i;
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@ -192,10 +124,15 @@ module system_top (
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assign gp_out[42:42] = (gpio_o[61] == 1'b1) ? clk_out : gp_out_s[42:42];
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assign gp_out[41: 0] = gp_out_s[41: 0];
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assign gp_in_s[95:93] = 3'd0;
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assign gp_in_s[92:92] = gp_in_1;
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assign gp_in_s[91:88] = gp_in_mio;
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assign gp_in_s[87: 0] = gp_in;
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assign gp_in_s[95:88] = gp_out_s[95:88];
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assign gp_in_s[87:66] = gp_in[87:66];
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assign gp_in_s[65:65] = gp_out_s[65];
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assign gp_in_s[64: 0] = gp_in[64:0];
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assign gp_misc_s[31: 9] = 23'd0;
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assign gp_misc_s[ 8: 8] = gp_in_1;
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assign gp_misc_s[ 7: 4] = 4'd0;
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assign gp_misc_s[ 3: 0] = gp_in_mio;
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// instantiations
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@ -249,29 +186,19 @@ module system_top (
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.gp_in_0 (gp_in_s[31:0]),
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.gp_in_1 (gp_in_s[63:32]),
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.gp_in_2 (gp_in_s[95:64]),
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.gp_in_3 (gp_misc_s),
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.gp_out_0 (gp_out_s[31:0]),
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.gp_out_1 (gp_out_s[63:32]),
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.gp_out_2 (gp_out_s[95:64]),
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.gp_out_3 (),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.gt_ref_clk (gt_ref_clk),
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.gt_rx_0_n (gt_rx_n[0]),
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.gt_rx_0_p (gt_rx_p[0]),
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.gt_rx_1_n (gt_rx_n[1]),
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.gt_rx_1_p (gt_rx_p[1]),
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.gt_rx_2_n (gt_rx_n[2]),
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.gt_rx_2_p (gt_rx_p[2]),
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.gt_rx_3_n (gt_rx_n[3]),
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.gt_rx_3_p (gt_rx_p[3]),
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.gt_tx_0_n (gt_tx_n[0]),
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.gt_tx_0_p (gt_tx_p[0]),
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.gt_tx_1_n (gt_tx_n[1]),
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.gt_tx_1_p (gt_tx_p[1]),
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.gt_tx_2_n (gt_tx_n[2]),
|
||||
.gt_tx_2_p (gt_tx_p[2]),
|
||||
.gt_tx_3_n (gt_tx_n[3]),
|
||||
.gt_tx_3_p (gt_tx_p[3]),
|
||||
.gt_rx_n (gt_rx_n),
|
||||
.gt_rx_p (gt_rx_p),
|
||||
.gt_tx_n (gt_tx_n),
|
||||
.gt_tx_p (gt_tx_p),
|
||||
.iic_main_scl_io (iic_scl),
|
||||
.iic_main_sda_io (iic_sda),
|
||||
.otg_vbusoc (1'b0),
|
||||
|
|
|
|||
Loading…
Reference in New Issue