util_do_ram: Fix Rx path for interrupted transfers
When capture length is not programmed the DMA will interrupt the transfer once it received all the samples he was set in its descriptor, this case must be handled by resetting the read process and returning an end of transfer (eot) to the data offload control logic.main
parent
1d4b27ea8c
commit
7a48f1beb9
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@ -182,7 +182,9 @@ module util_do_ram #(
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reg rd_active = 1'b0;
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reg [1:0] rd_req_cnt = 2'b0;
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always @(posedge m_axis_aclk) begin
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if (rd_request_valid & rd_request_ready)
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if (~rd_request_enable)
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rd_req_cnt <= 2'b0;
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else if (rd_request_valid & rd_request_ready)
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rd_req_cnt <= rd_req_cnt + 2'b1;
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else if (rd_response_eot)
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rd_req_cnt <= rd_req_cnt - 2'b1;
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@ -195,12 +197,17 @@ module util_do_ram #(
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rd_length <= rd_request_length[LENGTH_WIDTH-1:DST_ADDR_ALIGN];
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end
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wire rd_early_finish;
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assign rd_early_finish = rd_active & ~rd_request_enable;
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assign rd_last_beat = (rd_addr == rd_length) & rd_enable;
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assign rd_response_eot = m_axis_last & m_axis_valid & m_axis_ready;
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assign rd_response_eot = (m_axis_last & m_axis_valid & m_axis_ready) || rd_early_finish;
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// Read logic
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always @(posedge m_axis_aclk) begin
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if (rd_request_valid & rd_request_ready)
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if (~rd_request_enable)
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rd_active <= 1'b0;
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else if (rd_request_valid & rd_request_ready)
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rd_active <= 1'b1;
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else if (rd_last_beat)
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rd_active <= rd_req_cnt == 2;
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@ -253,7 +260,7 @@ module util_do_ram #(
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.M_AXIS_REGISTERED(0)
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) i_rd_fifo (
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.s_axis_aclk(m_axis_aclk),
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.s_axis_aresetn(m_axis_aresetn),
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.s_axis_aresetn(m_axis_aresetn & rd_request_enable),
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.s_axis_valid(rd_fifo_s_valid),
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.s_axis_ready(rd_fifo_s_ready),
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.s_axis_full(),
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@ -264,7 +271,7 @@ module util_do_ram #(
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.s_axis_almost_full(),
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.m_axis_aclk(m_axis_aclk),
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.m_axis_aresetn(m_axis_aresetn),
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.m_axis_aresetn(m_axis_aresetn & rd_request_enable),
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.m_axis_valid(m_axis_valid),
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.m_axis_ready(m_axis_ready),
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.m_axis_data({m_axis_last,m_axis_data}),
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