zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Revert "adrv9009: Removed ZC706 based project" 

This reverts commit 7e7f75c0270bb6793bedb339f62b67bab9d77a6e.
main
Laszlo Nagy 2018-09-27 10:46:39 +01:00 committed by Laszlo Nagy
parent fc74201c88
commit 7a5a8c5340
5 changed files with 507 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
projects/adrv9009/zc706/Makefile Normal file
View File

@ -0,0 +1,31 @@
####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := adrv9009_zc706
M_DEPS += ../common/adrv9009_bd.tcl
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../../common/zc706/zc706_plddr3_dacfifo_bd.tcl
M_DEPS += ../../common/zc706/zc706_plddr3_constr.xdc
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
LIB_DEPS += axi_adrv9009
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_spdif_tx
LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/axi_jesd204_tx
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += jesd204/jesd204_tx
LIB_DEPS += util_cpack
LIB_DEPS += util_upack
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/axi_dacfifo
LIB_DEPS += xilinx/util_adxcvr
include ../../scripts/project-xilinx.mk

15
projects/adrv9009/zc706/system_bd.tcl Normal file
View File

@ -0,0 +1,15 @@
set dac_fifo_name axi_adrv9009_dacfifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl
ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 250
source ../common/adrv9009_bd.tcl
ad_connect sys_dma_clk sys_ps7/FCLK_CLK2
ad_connect sys_ps7/FCLK_RESET2_N sys_dma_rstgen/ext_reset_in

79
projects/adrv9009/zc706/system_constr.xdc Normal file
View File

@ -0,0 +1,79 @@
# adrv9009
set_property -dict {PACKAGE_PIN AD10} [get_ports ref_clk0_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P (NC)
set_property -dict {PACKAGE_PIN AD9 } [get_ports ref_clk0_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N (NC)
set_property -dict {PACKAGE_PIN AA8 } [get_ports ref_clk1_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P
set_property -dict {PACKAGE_PIN AA7 } [get_ports ref_clk1_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N
set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[0]] ; ## A02 FMC_HPC_DP1_M2C_P
set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[0]] ; ## A03 FMC_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[1]] ; ## A06 FMC_HPC_DP2_M2C_P
set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[1]] ; ## A07 FMC_HPC_DP2_M2C_N
set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[2]] ; ## C06 FMC_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[2]] ; ## C07 FMC_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[0]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[0])
set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[0]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[0])
set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[1]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[3])
set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[1]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[3])
set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[2]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[2])
set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[2]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[2])
set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[3]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[1])
set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[3]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[1])
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVDS_25} [get_ports rx_os_sync_p] ; ## G27 FMC_HPC_LA25_P (Sniffer)
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVDS_25} [get_ports rx_os_sync_n] ; ## G28 FMC_HPC_LA25_N (Sniffer)
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_p] ; ## G06 FMC_HPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_n] ; ## G07 FMC_HPC_LA00_CC_N
set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_1_p] ; ## H28 FMC_HPC_LA24_P
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_1_n] ; ## H29 FMC_HPC_LA24_N
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_out_p] ; ## D08 FMC_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_out_n] ; ## D09 FMC_HPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9528] ; ## D15 FMC_HPC_LA09_N
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_csn_adrv9009] ; ## D14 FMC_HPC_LA09_P
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H13 FMC_HPC_LA07_P
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## H14 FMC_HPC_LA07_N
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## G12 FMC_HPC_LA08_P
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports ad9528_reset_b] ; ## D26 FMC_HPC_LA26_P
set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports ad9528_sysref_req] ; ## D27 FMC_HPC_LA26_N
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports adrv9009_tx1_enable] ; ## D17 FMC_HPC_LA13_P
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports adrv9009_tx2_enable] ; ## C18 FMC_HPC_LA14_P
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports adrv9009_rx1_enable] ; ## D18 FMC_HPC_LA13_N
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports adrv9009_rx2_enable] ; ## C19 FMC_HPC_LA14_N
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports adrv9009_test] ; ## D11 FMC_HPC_LA05_P
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports adrv9009_reset_b] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpint] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_00] ; ## H19 FMC_HPC_LA15_P
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_01] ; ## H20 FMC_HPC_LA15_N
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_02] ; ## G18 FMC_HPC_LA16_P
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_03] ; ## G19 FMC_HPC_LA16_N
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_04] ; ## H25 FMC_HPC_LA21_P
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_05] ; ## H26 FMC_HPC_LA21_N
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_06] ; ## C22 FMC_HPC_LA18_CC_P
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_07] ; ## C23 FMC_HPC_LA18_CC_N
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_08] ; ## G25 FMC_HPC_LA22_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_09] ; ## H22 FMC_HPC_LA19_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_10] ; ## H23 FMC_HPC_LA19_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_11] ; ## G21 FMC_HPC_LA20_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_12] ; ## G22 FMC_HPC_LA20_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_13] ; ## G31 FMC_HPC_LA29_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_14] ; ## G30 FMC_HPC_LA29_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_15] ; ## G24 FMC_HPC_LA22_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_16] ; ## G03 FMC_HPC_CLK1_M2C_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_17] ; ## G02 FMC_HPC_CLK1_M2C_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports adrv9009_gpio_18] ; ## D12 FMC_HPC_LA05_N
# clocks
create_clock -name tx_ref_clk -period 4.00 [get_ports ref_clk0_p]
create_clock -name rx_ref_clk -period 4.00 [get_ports ref_clk1_p]
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
create_clock -name rx_os_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_adrv9009_xcvr/inst/i_xch_2/i_gtxe2_channel/RXOUTCLK]

18
projects/adrv9009/zc706/system_project.tcl Normal file
View File

@ -0,0 +1,18 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_xilinx adrv9009_zc706
adi_project_files adrv9009_zc706 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zc706/zc706_plddr3_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
adi_project_run adrv9009_zc706

364
projects/adrv9009/zc706/system_top.v Normal file
View File

@ -0,0 +1,364 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [14:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [23:0] hdmi_data,
output spdif,
inout iic_scl,
inout iic_sda,
input ref_clk0_p,
input ref_clk0_n,
input ref_clk1_p,
input ref_clk1_n,
input [ 3:0] rx_data_p,
input [ 3:0] rx_data_n,
output [ 3:0] tx_data_p,
output [ 3:0] tx_data_n,
output rx_sync_p,
output rx_sync_n,
output rx_os_sync_p,
output rx_os_sync_n,
input tx_sync_p,
input tx_sync_n,
input tx_sync_1_p,
input tx_sync_1_n,
input sysref_p,
input sysref_n,
output sysref_out_p,
output sysref_out_n,
output spi_csn_ad9528,
output spi_csn_adrv9009,
output spi_clk,
output spi_mosi,
input spi_miso,
inout ad9528_reset_b,
inout ad9528_sysref_req,
inout adrv9009_tx1_enable,
inout adrv9009_tx2_enable,
inout adrv9009_rx1_enable,
inout adrv9009_rx2_enable,
inout adrv9009_test,
inout adrv9009_reset_b,
inout adrv9009_gpint,
inout adrv9009_gpio_00,
inout adrv9009_gpio_01,
inout adrv9009_gpio_02,
inout adrv9009_gpio_03,
inout adrv9009_gpio_04,
inout adrv9009_gpio_05,
inout adrv9009_gpio_06,
inout adrv9009_gpio_07,
inout adrv9009_gpio_15,
inout adrv9009_gpio_08,
inout adrv9009_gpio_09,
inout adrv9009_gpio_10,
inout adrv9009_gpio_11,
inout adrv9009_gpio_12,
inout adrv9009_gpio_14,
inout adrv9009_gpio_13,
inout adrv9009_gpio_17,
inout adrv9009_gpio_16,
inout adrv9009_gpio_18,
input sys_rst,
input sys_clk_p,
input sys_clk_n,
output [13:0] ddr3_addr,
output [ 2:0] ddr3_ba,
output ddr3_cas_n,
output [ 0:0] ddr3_ck_n,
output [ 0:0] ddr3_ck_p,
output [ 0:0] ddr3_cke,
output [ 0:0] ddr3_cs_n,
output [ 7:0] ddr3_dm,
inout [63:0] ddr3_dq,
inout [ 7:0] ddr3_dqs_n,
inout [ 7:0] ddr3_dqs_p,
output [ 0:0] ddr3_odt,
output ddr3_ras_n,
output ddr3_reset_n,
output ddr3_we_n);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire ref_clk0;
wire ref_clk1;
wire rx_sync;
wire rx_os_sync;
wire tx_sync;
wire tx_sync_1;
wire sysref;
wire sysref_out;
assign sysref_out = 0;
assign gpio_i[63:60] = gpio_o[63:60];
assign gpio_i[31:15] = gpio_o[31:15];
// instantiations
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (ref_clk0_p),
.IB (ref_clk0_n),
.O (ref_clk0),
.ODIV2 ());
IBUFDS_GTE2 i_ibufds_ref_clk1 (
.CEB (1'd0),
.I (ref_clk1_p),
.IB (ref_clk1_n),
.O (ref_clk1),
.ODIV2 ());
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
OBUFDS i_obufds_rx_os_sync (
.I (rx_os_sync),
.O (rx_os_sync_p),
.OB (rx_os_sync_n));
OBUFDS i_obufds_sysref_out (
.I (sysref_out),
.O (sysref_out_p),
.OB (sysref_out_n));
IBUFDS i_ibufds_tx_sync (
.I (tx_sync_p),
.IB (tx_sync_n),
.O (tx_sync));
IBUFDS i_ibufds_tx_sync_1 (
.I (tx_sync_1_p),
.IB (tx_sync_1_n),
.O (tx_sync_1));
IBUFDS i_ibufds_sysref (
.I (sysref_p),
.IB (sysref_n),
.O (sysref));
ad_iobuf #(.DATA_WIDTH(28)) i_iobuf (
.dio_t ({gpio_t[59:32]}),
.dio_i ({gpio_o[59:32]}),
.dio_o ({gpio_i[59:32]}),
.dio_p ({ ad9528_reset_b, // 59
ad9528_sysref_req, // 58
adrv9009_tx1_enable, // 57
adrv9009_tx2_enable, // 56
adrv9009_rx1_enable, // 55
adrv9009_rx2_enable, // 54
adrv9009_test, // 53
adrv9009_reset_b, // 52
adrv9009_gpint, // 51
adrv9009_gpio_00, // 50
adrv9009_gpio_01, // 49
adrv9009_gpio_02, // 48
adrv9009_gpio_03, // 47
adrv9009_gpio_04, // 46
adrv9009_gpio_05, // 45
adrv9009_gpio_06, // 44
adrv9009_gpio_07, // 43
adrv9009_gpio_15, // 42
adrv9009_gpio_08, // 41
adrv9009_gpio_09, // 40
adrv9009_gpio_10, // 39
adrv9009_gpio_11, // 38
adrv9009_gpio_12, // 37
adrv9009_gpio_14, // 36
adrv9009_gpio_13, // 35
adrv9009_gpio_17, // 34
adrv9009_gpio_16, // 33
adrv9009_gpio_18})); // 32
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.dac_fifo_bypass (gpio_o[60]),
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.rx_data_0_n (rx_data_n[0]),
.rx_data_0_p (rx_data_p[0]),
.rx_data_1_n (rx_data_n[1]),
.rx_data_1_p (rx_data_p[1]),
.rx_data_2_n (rx_data_n[2]),
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_ref_clk_0 (ref_clk1),
.rx_ref_clk_2 (ref_clk1),
.rx_sync_0 (rx_sync),
.rx_sync_2 (rx_os_sync),
.rx_sysref_0 (sysref),
.rx_sysref_2 (sysref),
.spdif (spdif),
.spi0_clk_i (spi_clk),
.spi0_clk_o (spi_clk),
.spi0_csn_0_o (spi_csn_adrv9009),
.spi0_csn_1_o (spi_csn_ad9528),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi_miso),
.spi0_sdo_i (spi_mosi),
.spi0_sdo_o (spi_mosi),
.spi1_clk_i (1'd0),
.spi1_clk_o (),
.spi1_csn_0_o (),
.spi1_csn_1_o (),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'd0),
.spi1_sdo_i (1'd0),
.spi1_sdo_o (),
.sys_clk_clk_n (sys_clk_n),
.sys_clk_clk_p (sys_clk_p),
.sys_rst(sys_rst),
.tx_data_0_n (tx_data_n[0]),
.tx_data_0_p (tx_data_p[0]),
.tx_data_1_n (tx_data_n[1]),
.tx_data_1_p (tx_data_p[1]),
.tx_data_2_n (tx_data_n[2]),
.tx_data_2_p (tx_data_p[2]),
.tx_data_3_n (tx_data_n[3]),
.tx_data_3_p (tx_data_p[3]),
.tx_ref_clk_0 (ref_clk1),
.tx_sync_0 (tx_sync),
.tx_sysref_0 (sysref));
endmodule
// ***************************************************************************
// ***************************************************************************