From 7a8dc92b848bcdc8a88a9f3e9a0519c573e4a90f Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 6 Dec 2016 11:55:28 +0200 Subject: [PATCH] usb_fx3: Add interrupt monitor and increase ILA data depth --- projects/usb_fx3/common/usb_fx3_bd.tcl | 10 +- projects/usb_fx3/zc706/system_top.v | 145 ++++++++----------------- 2 files changed, 49 insertions(+), 106 deletions(-) diff --git a/projects/usb_fx3/common/usb_fx3_bd.tcl b/projects/usb_fx3/common/usb_fx3_bd.tcl index 9091adbae..3cf47338a 100644 --- a/projects/usb_fx3/common/usb_fx3_bd.tcl +++ b/projects/usb_fx3/common/usb_fx3_bd.tcl @@ -15,8 +15,6 @@ create_bd_port -dir O slwr_n create_bd_port -dir O pktend_n create_bd_port -dir O epswitch_n -set_property -dict [list CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1}] $sys_ps7 - set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart] set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart @@ -30,6 +28,8 @@ set_property -dict [list CONFIG.c_sg_length_width {16}] $axi_usb_fx3_dma set usb_fx3_rx_axis_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 usb_fx3_rx_axis_fifo ] +set intr_monitor [ create_bd_cell -type ip -vlnv analog.com:user:axi_intr_monitor:1.0 intr_monitor ] + ad_connect axi_usb_fx3/s_axis axi_usb_fx3_dma/M_AXIS_MM2S ad_connect sys_cpu_clk usb_fx3_rx_axis_fifo/s_axis_aclk @@ -57,15 +57,17 @@ ad_connect axi_usb_fx3/slwr_n slwr_n ad_connect axi_usb_fx3/pktend_n pktend_n ad_connect axi_usb_fx3/epswitch_n epswitch_n - ad_cpu_interrupt ps-13 mb-12 axi_usb_fx3/irq ad_cpu_interrupt ps-12 mb-13 axi_usb_fx3_dma/mm2s_introut ad_cpu_interrupt ps-11 mb-14 axi_usb_fx3_dma/s2mm_introut ad_cpu_interrupt ps-10 mb-15 axi_uart/interrupt +ad_cpu_interrupt ps-9 mb-16 intr_monitor/irq ad_cpu_interconnect 0x50000000 axi_usb_fx3 ad_cpu_interconnect 0x40400000 axi_usb_fx3_dma ad_cpu_interconnect 0x40600000 axi_uart +ad_cpu_interconnect 0x43c00000 intr_monitor + ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 ad_mem_hp1_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_SG ad_mem_hp1_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_MM2S @@ -82,7 +84,7 @@ set_property -dict [list CONFIG.C_PROBE3_WIDTH {2}] $ila set_property -dict [list CONFIG.C_PROBE2_WIDTH {15}] $ila set_property -dict [list CONFIG.C_PROBE1_WIDTH {74}] $ila set_property -dict [list CONFIG.C_PROBE0_WIDTH {75}] $ila -set_property -dict [list CONFIG.C_DATA_DEPTH {32768}] $ila +set_property -dict [list CONFIG.C_DATA_DEPTH {65536}] $ila set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila set_property -dict [list CONFIG.C_PROBE2_MU_CNT {2}] $ila set_property -dict [list CONFIG.C_PROBE1_MU_CNT {2}] $ila diff --git a/projects/usb_fx3/zc706/system_top.v b/projects/usb_fx3/zc706/system_top.v index 8a212e3ca..030872a4d 100644 --- a/projects/usb_fx3/zc706/system_top.v +++ b/projects/usb_fx3/zc706/system_top.v @@ -34,122 +34,64 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps module system_top ( - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, - gpio_bd, + inout [14:0] gpio_bd, - usb_fx3_uart_tx, - usb_fx3_uart_rx, + input usb_fx3_uart_tx, + output usb_fx3_uart_rx, -// dma_rdy, -// dma_wmk, - fifo_rdy, + input [ 3:0] fifo_rdy, - data, - addr, - pclk, - slcs_n, - slrd_n, - sloe_n, - slwr_n, - //epswitch_n, - pktend_n, + inout [31:0] data, + output [1:0] addr, + output pclk, + output slcs_n, + output slrd_n, + output sloe_n, + output slwr_n, + output pktend_n, - pmode, + output [ 1:0] pmode, - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [23:0] hdmi_data, - spdif, + output spdif, - iic_scl, - iic_sda); + inout iic_scl, + inout iic_sda - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - input usb_fx3_uart_tx; - output usb_fx3_uart_rx; - -// input dma_rdy; -// input dma_wmk; - input [ 3:0] fifo_rdy; - - inout [31:0] data; - output [1:0] addr; - output pclk; - output slcs_n; - output slrd_n; - output sloe_n; - output slwr_n; - //output epswitch_n; - output pktend_n; - - output [ 1:0] pmode; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; +); // internal signals @@ -225,7 +167,6 @@ module system_top ( .ps_intr_06 (1'b0), .ps_intr_07 (1'b0), .ps_intr_08 (1'b0), - .ps_intr_09 (1'b0), .spdif (spdif)); endmodule