library/common/up_adc_common.v: Remove tabs
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@ -216,8 +216,8 @@ module up_adc_common #(
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h11)) begin
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up_adc_sdr_ddr_n <= up_wdata[16];
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up_adc_symb_op <= up_wdata[15];
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up_adc_symb_8_16b <= up_wdata[14];
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up_adc_symb_op <= up_wdata[15];
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up_adc_symb_8_16b <= up_wdata[14];
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up_adc_num_lanes <= up_wdata[12:8];
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up_adc_sref_sync <= up_wdata[4];
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up_adc_r1_mode <= up_wdata[2];
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@ -399,7 +399,7 @@ module up_adc_common #(
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7'h07: up_rdata_int <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8]
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7'h10: up_rdata_int <= {29'd0, up_adc_clk_enb, up_mmcm_resetn, up_resetn};
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7'h11: up_rdata_int <= {15'd0, up_adc_sdr_ddr_n,
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up_adc_symb_op, up_adc_symb_8_16b,
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up_adc_symb_op, up_adc_symb_8_16b,
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1'd0, up_adc_num_lanes,
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3'd0, up_adc_sref_sync,
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up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode};
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@ -440,7 +440,7 @@ module up_adc_common #(
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.up_clk (up_clk),
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.up_data_cntrl ({ up_adc_sdr_ddr_n,
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up_adc_symb_op,
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up_adc_symb_8_16b,
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up_adc_symb_8_16b,
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up_adc_num_lanes,
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up_adc_sref_sync,
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up_adc_sync,
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@ -454,7 +454,7 @@ module up_adc_common #(
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.d_clk (adc_clk),
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.d_data_cntrl ({ adc_sdr_ddr_n,
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adc_symb_op,
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adc_symb_8_16b,
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adc_symb_8_16b,
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adc_num_lanes,
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adc_sref_sync,
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adc_sync,
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