Add ad_dds.v
It will act as a wrapper for the previous dds modules(phase to angle conv.) this module will furthermore contain the phase accumulator logic.main
AndreiGrozav
AndreiGrozav
parent
35e8454fe7
commit
7b553997ab
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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// single channel dds (dual tone)
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module ad_dds #(
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parameter DISABLE = 0,
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// range 8-24
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parameter DDS_DW = 16,
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// range 8-16 (FIX ME)
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parameter PHASE_DW = 16,
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// set 1 for CORDIC or 2 for Polynomial
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parameter DDS_TYPE = 1,
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// range 8-24
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parameter CORDIC_DW = 16,
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// range 8-24 (make sure CORDIC_PHASE_DW < CORDIC_DW)
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parameter CORDIC_PHASE_DW = 16,
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// the clock radtio between the device clock(sample rate) and the dac_core clock
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parameter CLK_RATIO = 1) (
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// interface
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input clk,
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input rst,
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input dac_dds_format,
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input dac_data_sync,
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input [ 15:0] tone_1_scale,
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input [ 15:0] tone_2_scale,
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input [ 15:0] tone_1_init_offset,
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input [ 15:0] tone_2_init_offset,
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input [ PHASE_DW-1:0] tone_1_freq_word,
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input [ PHASE_DW-1:0] tone_2_freq_word,
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output reg [DDS_DW*CLK_RATIO-1:0] dac_dds_data
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);
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// internal registers
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reg [PHASE_DW-1:0] dac_dds_incr_0 = 'd0;
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reg [PHASE_DW-1:0] dac_dds_incr_1 = 'd0;
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// dds solution
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genvar i;
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generate
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if (DISABLE == 1) begin
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always @(posedge clk) begin
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dac_dds_data <= {(DDS_DW*CLK_RATIO-1){1'b0}};
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end
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end else begin
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// enable dds
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reg [PHASE_DW-1:0] dac_dds_phase_0[1:CLK_RATIO];
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reg [PHASE_DW-1:0] dac_dds_phase_1[1:CLK_RATIO];
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wire [ DDS_DW-1:0] dac_dds_data_s[1:CLK_RATIO];
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for (i=1; i <= CLK_RATIO; i=i+1) begin: dds_phase
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always @(posedge clk) begin
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if (dac_data_sync == 1'b1) begin
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dac_dds_data[DDS_DW*i-1:DDS_DW*(i-1)] <= {(DDS_DW-1){1'b0}};
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end else begin
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dac_dds_data[DDS_DW*i-1:DDS_DW*(i-1)] <= dac_dds_data_s[i];
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end
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end
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// phase accumulator
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always @(posedge clk) begin
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// phase incrementaion accross 2^N (0<N<5) phase clock ratio
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dac_dds_incr_0 <= tone_1_freq_word * CLK_RATIO;
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dac_dds_incr_1 <= tone_2_freq_word * CLK_RATIO;
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if (dac_data_sync == 1'b1) begin
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if (i == 1) begin
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dac_dds_phase_0[1] <= tone_1_init_offset;
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dac_dds_phase_1[1] <= tone_2_init_offset;
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end else begin
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dac_dds_phase_0[i] <= dac_dds_phase_0[i-1] + tone_1_freq_word;
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dac_dds_phase_1[i] <= dac_dds_phase_1[i-1] + tone_2_freq_word;
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end
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end else begin
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dac_dds_phase_0[i] <= dac_dds_phase_0[i] + dac_dds_incr_0;
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dac_dds_phase_1[i] <= dac_dds_phase_1[i] + dac_dds_incr_1;
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end
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end
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// phase to amplitude convertor
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ad_dds_2 #(
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.DDS_DW (DDS_DW),
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.DDS_TYPE (DDS_TYPE),
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.CORDIC_DW (CORDIC_DW),
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.CORDIC_PHASE_DW (CORDIC_PHASE_DW))
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i_dds_2 (
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.clk (clk),
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.dds_format (dac_dds_format),
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.dds_phase_0 (dac_dds_phase_0[i]),
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.dds_scale_0 (tone_1_scale),
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.dds_phase_1 (dac_dds_phase_1[i]),
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.dds_scale_1 (tone_2_scale),
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.dds_data (dac_dds_data_s[i])
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);
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end
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end
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endgenerate
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endmodule
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@ -57,12 +57,9 @@ module ad_dds_1 #(
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// internal signals
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wire [ DDS_D_DW-1:0] sine_s;
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wire [ 3:0] zeros;
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wire [ DDS_D_DW-1:0] sine_s;
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wire [DDS_D_DW+17:0] s1_data_s;
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assign zeros = 0;
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// sine
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generate
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@ -70,12 +67,12 @@ module ad_dds_1 #(
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// the cordic module input angle width must be equal with it's width
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// at this point the phase is only generated on 16 bits
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wire [CORDIC_PHASE_DW:0] angle_s;
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wire [DDS_P_DW-1:0] angle_s;
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if (CORDIC_PHASE_DW >= 16) begin
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assign angle_s = {angle,{CORDIC_PHASE_DW-15{1'b0}}};
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if (DDS_P_DW >= 16) begin
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assign angle_s = {angle,{DDS_P_DW-15{1'b0}}};
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end else begin
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assign angle_s = {angle[15:16-CORDIC_PHASE_DW],1'b0};
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assign angle_s = {angle[15:16-DDS_P_DW],1'b0};
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end
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ad_dds_sine_cordic #(
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@ -84,7 +81,7 @@ module ad_dds_1 #(
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.DELAY_DW(1))
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i_dds_sine (
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.clk (clk),
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.angle (angle),
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.angle (angle_s),
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.sine (sine_s),
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.cosine (),
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.ddata_in (1'b0),
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@ -35,7 +35,7 @@
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`timescale 1ns/100ps
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module ad_dds #(
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module ad_dds_2 #(
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// Disable DDS
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parameter DISABLE = 0,
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@ -124,8 +124,8 @@ module ad_dds #(
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ad_dds_1 #(
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.DDS_TYPE(DDS_TYPE),
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.CORDIC_DW(CORDIC_DW),
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.CORDIC_PHASE_DW(CORDIC_PHASE_DW))
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.DDS_D_DW(CORDIC_DW),
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.DDS_P_DW(CORDIC_PHASE_DW))
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i_dds_1_0 (
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.clk (clk),
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.angle (dds_phase_0),
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@ -136,8 +136,8 @@ module ad_dds #(
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ad_dds_1 #(
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.DDS_TYPE(DDS_TYPE),
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.CORDIC_DW(CORDIC_DW),
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.CORDIC_PHASE_DW(CORDIC_PHASE_DW))
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.DDS_D_DW(DDS_D_DW),
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.DDS_P_DW(DDS_P_DW))
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i_dds_1_1 (
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.clk (clk),
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.angle (dds_phase_1),
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