From 7c3b4a5c733449f4e924ac4693090fac0568ce85 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Mon, 9 Sep 2019 12:43:09 +0100 Subject: [PATCH] ad9208_dual_ebz: Cleanup workarounds Cleanup placement constraints and let the tool have more freedom to place and route the design. This is possible only after balancing the memory and system clocks. --- projects/ad9208_dual_ebz/vcu118/system_bd.tcl | 7 ------- .../ad9208_dual_ebz/vcu118/system_constr.xdc | 17 ----------------- 2 files changed, 24 deletions(-) diff --git a/projects/ad9208_dual_ebz/vcu118/system_bd.tcl b/projects/ad9208_dual_ebz/vcu118/system_bd.tcl index f4e85bc5d..817575364 100644 --- a/projects/ad9208_dual_ebz/vcu118/system_bd.tcl +++ b/projects/ad9208_dual_ebz/vcu118/system_bd.tcl @@ -34,10 +34,3 @@ foreach i {0 1} { } -# Set the smart interconnect to use a lower speed switch to meet timing -set_property -dict [list CONFIG.ADVANCED_PROPERTIES { __view__ { \ - timing { M00_Buffer { AR_SLR_PIPE 1 AW_SLR_PIPE 1 B_SLR_PIPE 1 R_SLR_PIPE 1 W_SLR_PIPE 1 } } \ - clocking { SW0 { ASSOCIATED_CLK aclk1 } } \ - } }] [get_bd_cells axi_mem_interconnect] - - diff --git a/projects/ad9208_dual_ebz/vcu118/system_constr.xdc b/projects/ad9208_dual_ebz/vcu118/system_constr.xdc index a75f9a111..7a764b479 100644 --- a/projects/ad9208_dual_ebz/vcu118/system_constr.xdc +++ b/projects/ad9208_dual_ebz/vcu118/system_constr.xdc @@ -89,20 +89,3 @@ set_input_delay -clock [get_clocks global_clk_0] \ [expr [get_property PERIOD [get_clocks global_clk_0]] / 2] \ [get_ports {rx_sysref_*}] -# Place the sysref capture FFs near Bank 43, they can't be placed into the IOB due pulse width violation. -# Creating the pblock prevents the tool from placing the FFs on another SLR and not closing timing. -create_pblock pblock_sysref -resize_pblock pblock_sysref -add SLICE_X50Y254:SLICE_X50Y278 -add_cells_to_pblock pblock_sysref [get_cells \ - [list i_system_wrapper/system_i/axi_ad9208_1_jesd/rx/inst/i_lmfc/sysref_r_reg \ - i_system_wrapper/system_i/axi_ad9208_0_jesd/rx/inst/i_lmfc/sysref_r_reg]] - -# Place the data path in SLR1 for a better timing closure -create_pblock adc_data_path -resize_pblock adc_data_path -add CLOCKREGION_X0Y5:CLOCKREGION_X2Y9 -add_cells_to_pblock adc_data_path [get_cells \ - [list i_system_wrapper/system_i/util_ad9208_cpack \ - i_system_wrapper/system_i/rx_ad9208_0_tpl_core \ - i_system_wrapper/system_i/rx_ad9208_1_tpl_core \ - i_system_wrapper/system_i/axi_ad9208_dma \ - i_system_wrapper/system_i/axi_ad9208_fifo]] -clear_locs