From 7c541c704a36a6f0b8c97bd7fde589ac621ecfa9 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 14 Oct 2016 18:08:08 +0300 Subject: [PATCH] usdrx1: ZC706, Update project to the new GT framework --- projects/usdrx1/common/usdrx1_bd.tcl | 202 +++++++----------------- projects/usdrx1/zc706/Makefile | 12 +- projects/usdrx1/zc706/system_constr.xdc | 2 +- projects/usdrx1/zc706/system_top.v | 39 +++-- 4 files changed, 81 insertions(+), 174 deletions(-) diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl index 4b9f89177..c6cdbd191 100644 --- a/projects/usdrx1/common/usdrx1_bd.tcl +++ b/projects/usdrx1/common/usdrx1_bd.tcl @@ -9,12 +9,6 @@ create_bd_port -dir I spi_sdo_i create_bd_port -dir O spi_sdo_o create_bd_port -dir I spi_sdi_i -create_bd_port -dir I rx_ref_clk -create_bd_port -dir O rx_sync -create_bd_port -dir O rx_sysref -create_bd_port -dir I -from 7 -to 0 rx_data_p -create_bd_port -dir I -from 7 -to 0 rx_data_n - create_bd_port -dir O -from 255 -to 0 gt_rx_data create_bd_port -dir I -from 63 -to 0 gt_rx_data_0 create_bd_port -dir I -from 63 -to 0 gt_rx_data_1 @@ -58,82 +52,20 @@ set axi_ad9671_core_3 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671: set_property -dict [list CONFIG.QUAD_OR_DUAL_N {0}] $axi_ad9671_core_3 set_property -dict [list CONFIG.ID {3}] $axi_ad9671_core_3 -set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.2 axi_usdrx1_jesd] +set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_usdrx1_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd set_property -dict [list CONFIG.C_LANES {8}] $axi_usdrx1_jesd set_property -dict [list CONFIG.GT_Line_Rate {3.2} ] $axi_usdrx1_jesd set_property -dict [list CONFIG.GT_REFCLK_FREQ {80.000} ] $axi_usdrx1_jesd -set axi_usdrx1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_usdrx1_gt] -set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_usdrx1_gt -set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $axi_usdrx1_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_usdrx1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_0 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_0 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_0 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_usdrx1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_1 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_1 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_1 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_usdrx1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_2 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_2 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_2 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_usdrx1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_3 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_3 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_3 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_usdrx1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_4 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_OUT_DIV_4 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_OUT_DIV_4 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_4 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_4 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_usdrx1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_5 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_OUT_DIV_5 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_OUT_DIV_5 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_5 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_5 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_usdrx1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_6 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_OUT_DIV_6 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_OUT_DIV_6 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_6 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_6 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_usdrx1_gt -set_property -dict [list CONFIG.CPLL_FBDIV_7 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_OUT_DIV_7 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_OUT_DIV_7 {1}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_7 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_7 {4}] $axi_usdrx1_gt -set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_usdrx1_gt -set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_usdrx1_gt +set axi_usdrx1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_usdrx1_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_usdrx1_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_usdrx1_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_usdrx1_xcvr -set util_usdrx1_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_usdrx1_gt] -set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_usdrx1_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_usdrx1_gt -set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_usdrx1_gt -set_property -dict [list CONFIG.RX_ENABLE {1}] $util_usdrx1_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_usdrx1_gt -set_property -dict [list CONFIG.TX_ENABLE {0}] $util_usdrx1_gt +set util_usdrx1_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_usdrx1_xcvr] +set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_usdrx1_xcvr +set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_usdrx1_xcvr set axi_usdrx1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_usdrx1_dma] set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_usdrx1_dma @@ -154,6 +86,30 @@ set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_usdrx1_spi set_property -dict [list CONFIG.C_NUM_SS_BITS {5}] $axi_usdrx1_spi set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_usdrx1_spi +set data_slice_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_0] +set_property -dict [list CONFIG.DIN_WIDTH {256}] $data_slice_0 +set_property -dict [list CONFIG.DIN_TO {0}] $data_slice_0 +set_property -dict [list CONFIG.DIN_FROM {63}] $data_slice_0 +set_property -dict [list CONFIG.DOUT_WIDTH {64}] $data_slice_0 + +set data_slice_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_1] +set_property -dict [list CONFIG.DIN_WIDTH {256}] $data_slice_1 +set_property -dict [list CONFIG.DIN_TO {64}] $data_slice_1 +set_property -dict [list CONFIG.DIN_FROM {127}] $data_slice_1 +set_property -dict [list CONFIG.DOUT_WIDTH {64}] $data_slice_1 + +set data_slice_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_2] +set_property -dict [list CONFIG.DIN_WIDTH {256}] $data_slice_2 +set_property -dict [list CONFIG.DIN_TO {128}] $data_slice_2 +set_property -dict [list CONFIG.DIN_FROM {191}] $data_slice_2 +set_property -dict [list CONFIG.DOUT_WIDTH {64}] $data_slice_2 + +set data_slice_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 data_slice_3] +set_property -dict [list CONFIG.DIN_WIDTH {256}] $data_slice_3 +set_property -dict [list CONFIG.DIN_TO {192}] $data_slice_3 +set_property -dict [list CONFIG.DIN_FROM {255}] $data_slice_3 +set_property -dict [list CONFIG.DOUT_WIDTH {64}] $data_slice_3 + # connections (spi) ad_connect spi_csn_i axi_usdrx1_spi/ss_i @@ -165,78 +121,29 @@ ad_connect spi_sdo_o axi_usdrx1_spi/io0_o ad_connect spi_sdi_i axi_usdrx1_spi/io1_i ad_connect sys_cpu_clk axi_usdrx1_spi/ext_spi_clk -# connections (gt) - -ad_connect util_usdrx1_gt/qpll_ref_clk rx_ref_clk -ad_connect util_usdrx1_gt/cpll_ref_clk rx_ref_clk - -ad_connect axi_usdrx1_gt/gt_pll_0 util_usdrx1_gt/gt_pll_0 -ad_connect axi_usdrx1_gt/gt_pll_1 util_usdrx1_gt/gt_pll_1 -ad_connect axi_usdrx1_gt/gt_pll_2 util_usdrx1_gt/gt_pll_2 -ad_connect axi_usdrx1_gt/gt_pll_3 util_usdrx1_gt/gt_pll_3 -ad_connect axi_usdrx1_gt/gt_pll_4 util_usdrx1_gt/gt_pll_4 -ad_connect axi_usdrx1_gt/gt_pll_5 util_usdrx1_gt/gt_pll_5 -ad_connect axi_usdrx1_gt/gt_pll_6 util_usdrx1_gt/gt_pll_6 -ad_connect axi_usdrx1_gt/gt_pll_7 util_usdrx1_gt/gt_pll_7 - -ad_connect axi_usdrx1_gt/gt_rx_0 util_usdrx1_gt/gt_rx_0 -ad_connect axi_usdrx1_gt/gt_rx_1 util_usdrx1_gt/gt_rx_1 -ad_connect axi_usdrx1_gt/gt_rx_2 util_usdrx1_gt/gt_rx_2 -ad_connect axi_usdrx1_gt/gt_rx_3 util_usdrx1_gt/gt_rx_3 -ad_connect axi_usdrx1_gt/gt_rx_4 util_usdrx1_gt/gt_rx_4 -ad_connect axi_usdrx1_gt/gt_rx_5 util_usdrx1_gt/gt_rx_5 -ad_connect axi_usdrx1_gt/gt_rx_6 util_usdrx1_gt/gt_rx_6 -ad_connect axi_usdrx1_gt/gt_rx_7 util_usdrx1_gt/gt_rx_7 - -ad_connect axi_usdrx1_gt/gt_rx_ip_0 axi_usdrx1_jesd/gt0_rx -ad_connect axi_usdrx1_gt/gt_rx_ip_1 axi_usdrx1_jesd/gt1_rx -ad_connect axi_usdrx1_gt/gt_rx_ip_2 axi_usdrx1_jesd/gt2_rx -ad_connect axi_usdrx1_gt/gt_rx_ip_3 axi_usdrx1_jesd/gt3_rx -ad_connect axi_usdrx1_gt/gt_rx_ip_4 axi_usdrx1_jesd/gt4_rx -ad_connect axi_usdrx1_gt/gt_rx_ip_5 axi_usdrx1_jesd/gt5_rx -ad_connect axi_usdrx1_gt/gt_rx_ip_6 axi_usdrx1_jesd/gt6_rx -ad_connect axi_usdrx1_gt/gt_rx_ip_7 axi_usdrx1_jesd/gt7_rx - -ad_connect axi_usdrx1_gt/rx_gt_comma_align_enb_0 axi_usdrx1_jesd/rxencommaalign_out -ad_connect axi_usdrx1_gt/rx_gt_comma_align_enb_1 axi_usdrx1_jesd/rxencommaalign_out -ad_connect axi_usdrx1_gt/rx_gt_comma_align_enb_2 axi_usdrx1_jesd/rxencommaalign_out -ad_connect axi_usdrx1_gt/rx_gt_comma_align_enb_3 axi_usdrx1_jesd/rxencommaalign_out -ad_connect axi_usdrx1_gt/rx_gt_comma_align_enb_4 axi_usdrx1_jesd/rxencommaalign_out -ad_connect axi_usdrx1_gt/rx_gt_comma_align_enb_5 axi_usdrx1_jesd/rxencommaalign_out -ad_connect axi_usdrx1_gt/rx_gt_comma_align_enb_6 axi_usdrx1_jesd/rxencommaalign_out -ad_connect axi_usdrx1_gt/rx_gt_comma_align_enb_7 axi_usdrx1_jesd/rxencommaalign_out - # connections (adc) -ad_connect rx_data_p util_usdrx1_gt/rx_p -ad_connect rx_data_n util_usdrx1_gt/rx_n -ad_connect rx_sync util_usdrx1_gt/rx_sync -ad_connect rx_sysref util_usdrx1_gt/rx_ip_sysref +ad_xcvrcon util_usdrx1_xcvr axi_usdrx1_xcvr axi_usdrx1_jesd +ad_connect util_usdrx1_xcvr/rx_out_clk_0 axi_ad9671_core_0/rx_clk +ad_connect util_usdrx1_xcvr/rx_out_clk_0 axi_ad9671_core_1/rx_clk +ad_connect util_usdrx1_xcvr/rx_out_clk_0 axi_ad9671_core_2/rx_clk +ad_connect util_usdrx1_xcvr/rx_out_clk_0 axi_ad9671_core_3/rx_clk +ad_connect axi_usdrx1_jesd/rx_start_of_frame axi_ad9671_core_0/rx_sof +ad_connect axi_usdrx1_jesd/rx_start_of_frame axi_ad9671_core_1/rx_sof +ad_connect axi_usdrx1_jesd/rx_start_of_frame axi_ad9671_core_2/rx_sof +ad_connect axi_usdrx1_jesd/rx_start_of_frame axi_ad9671_core_3/rx_sof -ad_connect util_usdrx1_gt/rx_out_clk util_usdrx1_gt/rx_clk -ad_connect util_usdrx1_gt/rx_out_clk axi_usdrx1_jesd/rx_core_clk +ad_connect axi_usdrx1_jesd/rx_tdata data_slice_0/Din +ad_connect axi_usdrx1_jesd/rx_tdata data_slice_1/Din +ad_connect axi_usdrx1_jesd/rx_tdata data_slice_2/Din +ad_connect axi_usdrx1_jesd/rx_tdata data_slice_3/Din -ad_connect util_usdrx1_gt/rx_ip_rst axi_usdrx1_jesd/rx_reset -ad_connect util_usdrx1_gt/rx_ip_rst_done axi_usdrx1_jesd/rx_reset_done -ad_connect util_usdrx1_gt/rx_ip_sysref axi_usdrx1_jesd/rx_sysref -ad_connect util_usdrx1_gt/rx_ip_sync axi_usdrx1_jesd/rx_sync -ad_connect util_usdrx1_gt/rx_ip_sof axi_usdrx1_jesd/rx_start_of_frame -ad_connect util_usdrx1_gt/rx_ip_data axi_usdrx1_jesd/rx_tdata +ad_connect data_slice_0/Dout axi_ad9671_core_0/rx_data +ad_connect data_slice_1/Dout axi_ad9671_core_1/rx_data +ad_connect data_slice_2/Dout axi_ad9671_core_2/rx_data +ad_connect data_slice_3/Dout axi_ad9671_core_3/rx_data -ad_connect gt_rx_data util_usdrx1_gt/rx_data -ad_connect util_usdrx1_gt/rx_out_clk axi_ad9671_core_0/rx_clk -ad_connect gt_rx_data_0 axi_ad9671_core_0/rx_data -ad_connect util_usdrx1_gt/rx_sof axi_ad9671_core_0/rx_sof -ad_connect util_usdrx1_gt/rx_out_clk axi_ad9671_core_1/rx_clk -ad_connect gt_rx_data_1 axi_ad9671_core_1/rx_data -ad_connect util_usdrx1_gt/rx_sof axi_ad9671_core_1/rx_sof -ad_connect util_usdrx1_gt/rx_out_clk axi_ad9671_core_2/rx_clk -ad_connect gt_rx_data_2 axi_ad9671_core_2/rx_data -ad_connect util_usdrx1_gt/rx_sof axi_ad9671_core_2/rx_sof -ad_connect util_usdrx1_gt/rx_out_clk axi_ad9671_core_3/rx_clk -ad_connect gt_rx_data_3 axi_ad9671_core_3/rx_data -ad_connect util_usdrx1_gt/rx_sof axi_ad9671_core_3/rx_sof -ad_connect axi_ad9671_core_0/adc_clk usdrx1_fifo/adc_clk +ad_connect util_usdrx1_xcvr/rx_out_clk_0 usdrx1_fifo/adc_clk ad_connect adc_data_0 axi_ad9671_core_0/adc_data ad_connect adc_data_1 axi_ad9671_core_1/adc_data ad_connect adc_data_2 axi_ad9671_core_2/adc_data @@ -264,7 +171,8 @@ ad_connect axi_ad9671_adc_sync axi_ad9671_core_1/adc_sync_in ad_connect axi_ad9671_adc_sync axi_ad9671_core_2/adc_sync_in ad_connect axi_ad9671_adc_sync axi_ad9671_core_3/adc_sync_in -ad_connect util_usdrx1_gt/rx_rst usdrx1_fifo/adc_rst +ad_connect axi_usdrx1_jesd_rstgen/peripheral_reset usdrx1_fifo/adc_rst + ad_connect adc_dovf usdrx1_fifo/adc_wovf ad_connect usdrx1_fifo/dma_wdata axi_usdrx1_dma/s_axis_data @@ -281,7 +189,7 @@ ad_cpu_interconnect 0x44A10000 axi_ad9671_core_1 ad_cpu_interconnect 0x44A20000 axi_ad9671_core_2 ad_cpu_interconnect 0x44A30000 axi_ad9671_core_3 -ad_cpu_interconnect 0x44A60000 axi_usdrx1_gt +ad_cpu_interconnect 0x44A60000 axi_usdrx1_xcvr ad_cpu_interconnect 0x44A91000 axi_usdrx1_jesd ad_cpu_interconnect 0x7c400000 axi_usdrx1_dma ad_cpu_interconnect 0x7c420000 axi_usdrx1_spi @@ -291,7 +199,7 @@ ad_mem_hp2_interconnect sys_200m_clk axi_usdrx1_dma/m_dest_axi ad_connect sys_cpu_resetn axi_usdrx1_dma/m_dest_axi_aresetn ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect sys_cpu_clk axi_usdrx1_gt/m_axi +ad_mem_hp3_interconnect sys_cpu_clk axi_usdrx1_xcvr/m_axi #interrupts @@ -300,7 +208,7 @@ ad_cpu_interrupt ps-13 mb-13 axi_usdrx1_dma/irq # ila -set ila_ad9671 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_ad9671] +set ila_ad9671 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_ad9671] set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_ad9671 set_property -dict [list CONFIG.C_NUM_OF_PROBES {9}] $ila_ad9671 set_property -dict [list CONFIG.C_PROBE0_WIDTH {128}] $ila_ad9671 diff --git a/projects/usdrx1/zc706/Makefile b/projects/usdrx1/zc706/Makefile index c29b78937..e1acdb44d 100644 --- a/projects/usdrx1/zc706/Makefile +++ b/projects/usdrx1/zc706/Makefile @@ -21,12 +21,12 @@ M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl M_DEPS += ../../../library/axi_ad9671/axi_ad9671.xpr M_DEPS += ../../../library/xilinx/axi_adcfifo/axi_adcfifo.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_VIVADO := vivado -mode batch -source @@ -57,12 +57,12 @@ clean: clean-all:clean make -C ../../../library/axi_ad9671 clean make -C ../../../library/xilinx/axi_adcfifo clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_clkgen clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean - make -C ../../../library/axi_jesd_gt clean make -C ../../../library/axi_spdif_tx clean - make -C ../../../library/util_jesd_gt clean + make -C ../../../library/xilinx/util_adxcvr clean usdrx1_zc706.sdk/system_top.hdf: $(M_DEPS) @@ -73,12 +73,12 @@ usdrx1_zc706.sdk/system_top.hdf: $(M_DEPS) lib: make -C ../../../library/axi_ad9671 make -C ../../../library/xilinx/axi_adcfifo + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_clkgen make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx - make -C ../../../library/axi_jesd_gt make -C ../../../library/axi_spdif_tx - make -C ../../../library/util_jesd_gt + make -C ../../../library/xilinx/util_adxcvr #################################################################################### #################################################################################### diff --git a/projects/usdrx1/zc706/system_constr.xdc b/projects/usdrx1/zc706/system_constr.xdc index e86c8c2d2..a162916e4 100644 --- a/projects/usdrx1/zc706/system_constr.xdc +++ b/projects/usdrx1/zc706/system_constr.xdc @@ -82,4 +82,4 @@ set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports dac_data # clocks create_clock -name rx_ref_clk -period 12.50 [get_ports rx_ref_clk_p] -create_clock -name rx_div_clk -period 12.50 [get_nets i_system_wrapper/system_i/axi_usdrx1_gt_rx_clk] +create_clock -name rx_div_clk -period 12.50 [get_pins i_system_wrapper/system_i/util_usdrx1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] diff --git a/projects/usdrx1/zc706/system_top.v b/projects/usdrx1/zc706/system_top.v index f782ab0ae..082184c74 100644 --- a/projects/usdrx1/zc706/system_top.v +++ b/projects/usdrx1/zc706/system_top.v @@ -265,11 +265,6 @@ module system_top ( wire adc_dovf_1; wire adc_dovf_2; wire adc_dovf_3; - wire [255:0] gt_rx_data; - wire [63:0] gt_rx_data_0; - wire [63:0] gt_rx_data_1; - wire [63:0] gt_rx_data_2; - wire [63:0] gt_rx_data_3; wire [63:0] gpio_i; wire [63:0] gpio_o; wire [63:0] gpio_t; @@ -301,11 +296,6 @@ module system_top ( // single dma for all channels - assign gt_rx_data_3 = gt_rx_data[255:192]; - assign gt_rx_data_2 = gt_rx_data[191:128]; - assign gt_rx_data_1 = gt_rx_data[127: 64]; - assign gt_rx_data_0 = gt_rx_data[ 63: 0]; - assign adc_data = {adc_data_3, adc_data_2, adc_data_1, adc_data_0}; assign adc_valid = (|adc_valid_0) | (|adc_valid_1) | (|adc_valid_2) | (|adc_valid_3) ; assign adc_dovf_0 = adc_dovf; @@ -452,11 +442,6 @@ module system_top ( .adc_dovf_1 (adc_dovf_1), .adc_dovf_2 (adc_dovf_2), .adc_dovf_3 (adc_dovf_3), - .gt_rx_data (gt_rx_data), - .gt_rx_data_0 (gt_rx_data_0), - .gt_rx_data_1 (gt_rx_data_1), - .gt_rx_data_2 (gt_rx_data_2), - .gt_rx_data_3 (gt_rx_data_3), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), @@ -476,11 +461,25 @@ module system_top ( .ps_intr_09 (1'b0), .ps_intr_10 (1'b0), .ps_intr_11 (1'b0), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_data_2_n (rx_data_n[2]), + .rx_data_2_p (rx_data_p[2]), + .rx_data_3_n (rx_data_n[3]), + .rx_data_3_p (rx_data_p[3]), + .rx_data_4_n (rx_data_n[4]), + .rx_data_4_p (rx_data_p[4]), + .rx_data_5_n (rx_data_n[5]), + .rx_data_5_p (rx_data_p[5]), + .rx_data_6_n (rx_data_n[6]), + .rx_data_6_p (rx_data_p[6]), + .rx_data_7_n (rx_data_n[7]), + .rx_data_7_p (rx_data_p[7]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), .spdif (spdif), .spi_clk_i (spi_clk), .spi_clk_o (spi_clk),