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axi_ad9361&TDD: Update TDD 

+ Delete unnecessary registers
+ Add the module ad_addsub.v to resolve additions and subtractions inside TDD control
+ Redefine the burst logic
+ Redesign the control signal generations
+ Note: This patch fix the TDD related timing violations
main
Istvan Csomortani 2015-05-13 14:03:01 +03:00
parent a1d680ee6b
commit 7c9bc40c75
5 changed files with 440 additions and 194 deletions
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1
library/axi_ad9361/axi_ad9361_ip.tcl
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@ -17,6 +17,7 @@ adi_ip_files axi_ad9361 [list \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/ad_dcfilter.v" \
"$ad_hdl_dir/library/common/ad_iqcor.v" \
"$ad_hdl_dir/library/common/ad_addsub.v" \
"$ad_hdl_dir/library/common/ad_tdd_control.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \

8
library/axi_ad9361/axi_ad9361_tdd.v
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@ -109,11 +109,9 @@ module axi_ad9361_tdd (
wire rst;
wire tdd_start_s;
wire tdd_counter_reset_s;
wire tdd_update_regs_s;
wire tdd_secondary_s;
wire tdd_burst_en_s;
wire [ 5:0] tdd_burst_count_s;
wire tdd_infinite_burst_s;
wire [21:0] tdd_counter_init_s;
wire [21:0] tdd_frame_length_s;
wire [ 7:0] tdd_tx_dp_delay_s;
@ -138,7 +136,7 @@ module axi_ad9361_tdd (
wire [21:0] tdd_tx_dp_on_2_s;
wire [21:0] tdd_tx_dp_off_2_s;
wire [29:0] tdd_counter_status;
wire [23:0] tdd_counter_status;
assign tdd_dbg = {tdd_counter_status, tdd_enable, tdd_tx_dp_en,
tdd_rx_vco_en, tdd_tx_vco_en, tdd_rx_rf_en, tdd_tx_rf_en};
@ -151,11 +149,9 @@ module axi_ad9361_tdd (
.tdd_start(tdd_start_s),
.tdd_rst(rst),
.tdd_counter_reset(tdd_counter_reset_s),
.tdd_update_regs(tdd_update_regs_s),
.tdd_secondary(tdd_secondary_s),
.tdd_burst_en(tdd_burst_en_s),
.tdd_burst_count(tdd_burst_count_s),
.tdd_infinite_burst(tdd_infinite_burst_s),
.tdd_counter_init(tdd_counter_init_s),
.tdd_frame_length(tdd_frame_length_s),
.tdd_tx_dp_delay(tdd_tx_dp_delay_s),
@ -196,13 +192,11 @@ module axi_ad9361_tdd (
.rst(rst),
.tdd_start(tdd_start_s),
.tdd_counter_reset(tdd_counter_reset_s),
.tdd_update_regs(tdd_update_regs_s),
.tdd_secondary(tdd_secondary_s),
.tdd_counter_init(tdd_counter_init_s),
.tdd_frame_length(tdd_frame_length_s),
.tdd_burst_en(tdd_burst_en_s),
.tdd_burst_count(tdd_burst_count_s),
.tdd_infinite_burst(tdd_infinite_burst_s),
.tdd_tx_dp_delay(tdd_tx_dp_delay_s),
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),

132
library/common/ad_addsub.v Normal file
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@ -0,0 +1,132 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// A simple adder/substracter width preconfigured input ports width and overflow value
// Output = A - B or A + B
// Constraints: Awidth >= Bwidth
`timescale 1ns/1ps
module ad_addsub (
clk,
A,
overflow,
out,
CE
);
// parameters
parameter A_WIDTH = 32;
parameter CONST_VALUE = 32'h1;
parameter ADD_SUB = 0;
localparam ADDER = 0;
localparam SUBSTRACTER = 1;
// I/O definitions
input clk;
input [(A_WIDTH-1):0] A;
input [(A_WIDTH-1):0] overflow;
output [(A_WIDTH-1):0] out;
input CE;
// registers
reg [(A_WIDTH-1):0] out = 'b0;
reg [A_WIDTH:0] out_d = 'b0;
reg [A_WIDTH:0] out_d2 = 'b0;
reg [(A_WIDTH-1):0] A_d = 'b0;
reg [(A_WIDTH-1):0] A_d2 = 'b0;
reg [(A_WIDTH-1):0] overflow_d = 'b0;
reg [(A_WIDTH-1):0] overflow_d2 = 'b0;
// constant regs
reg [(A_WIDTH-1):0] B_reg = CONST_VALUE;
// latch the inputs
always @(posedge clk) begin
A_d <= A;
A_d2 <= A_d;
overflow_d <= overflow;
overflow_d2 <= overflow_d;
end
// ADDER/SUBSTRACTER
always @(posedge clk) begin
if ( ADD_SUB == ADDER ) begin
out_d <= A_d + B_reg;
end else begin
out_d <= A_d - B_reg;
end
end
// Resolve overflow
always @(posedge clk) begin
if ( ADD_SUB == ADDER ) begin
if ( out_d > overflow_d2 ) begin
out_d2 <= out_d - overflow_d2;
end else begin
out_d2 <= out_d;
end
end else begin // SUBSTRACTER
if ( out_d[A_WIDTH] == 1'b1 ) begin
out_d2 <= overflow_d2 + out_d;
end else begin
out_d2 <= out_d;
end
end
end
// output logic
always @(posedge clk) begin
if ( CE ) begin
out <= out_d2;
end else begin
out <= 'b0;
end
end
endmodule

460
library/common/ad_tdd_control.v
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@ -50,13 +50,11 @@ module ad_tdd_control(
tdd_start,
tdd_counter_reset,
tdd_update_regs,
tdd_secondary,
tdd_counter_init,
tdd_frame_length,
tdd_burst_en,
tdd_burst_count,
tdd_infinite_burst,
tdd_tx_dp_delay,
tdd_vco_rx_on_1,
@ -108,12 +106,10 @@ module ad_tdd_control(
input tdd_start;
input tdd_secondary;
input tdd_counter_reset;
input tdd_update_regs;
input [21:0] tdd_counter_init;
input [21:0] tdd_frame_length;
input tdd_burst_en;
input [ 5:0] tdd_burst_count;
input tdd_infinite_burst;
input [ 7:0] tdd_tx_dp_delay;
input [21:0] tdd_vco_rx_on_1;
@ -152,41 +148,6 @@ module ad_tdd_control(
// tdd control related
reg tdd_secondary_d = 1'h0;
reg tdd_start_d = 1'h0;
reg [21:0] tdd_counter_init_d = 22'h0;
reg [21:0] tdd_frame_length_d = 22'h0;
reg tdd_burst_en_d = 1'h0;
reg [ 5:0] tdd_burst_count_d = 5'h0;
reg tdd_infinite_burst_d = 1'h0;
reg [ 7:0] tdd_tx_dp_delay_d = 8'h0;
reg [21:0] tdd_vco_rx_on_1_d = 22'h0;
reg [21:0] tdd_vco_rx_off_1_d = 22'h0;
reg [21:0] tdd_vco_tx_on_1_d = 22'h0;
reg [21:0] tdd_vco_tx_off_1_d = 22'h0;
reg [21:0] tdd_rx_on_1_d = 22'h0;
reg [21:0] tdd_rx_off_1_d = 22'h0;
reg [21:0] tdd_tx_on_1_d = 22'h0;
reg [21:0] tdd_tx_off_1_d = 22'h0;
reg [21:0] tdd_tx_dp_on_1_d = 22'h0;
reg [21:0] tdd_tx_dp_off_1_d = 22'h0;
reg [21:0] tdd_vco_rx_on_2_d = 22'h0;
reg [21:0] tdd_vco_rx_off_2_d = 22'h0;
reg [21:0] tdd_vco_tx_on_2_d = 22'h0;
reg [21:0] tdd_vco_tx_off_2_d = 22'h0;
reg [21:0] tdd_rx_on_2_d = 22'h0;
reg [21:0] tdd_rx_off_2_d = 22'h0;
reg [21:0] tdd_tx_on_2_d = 22'h0;
reg [21:0] tdd_tx_off_2_d = 22'h0;
reg [21:0] tdd_tx_dp_on_2_d = 22'h0;
reg [21:0] tdd_tx_dp_off_2_d = 22'h0;
reg tdd_tx_dp_en = 1'b0;
reg tdd_rx_vco_en = 1'b0;
reg tdd_tx_vco_en = 1'b0;
@ -199,78 +160,38 @@ module ad_tdd_control(
reg [ 5:0] tdd_burst_counter = 6'h0;
reg tdd_counter_state = OFF;
reg tdd_burst_state = OFF;
reg counter_at_tdd_vco_rx_on_1 = 1'b0;
reg counter_at_tdd_vco_rx_off_1 = 1'b0;
reg counter_at_tdd_vco_tx_on_1 = 1'b0;
reg counter_at_tdd_vco_tx_off_1 = 1'b0;
reg counter_at_tdd_rx_on_1 = 1'b0;
reg counter_at_tdd_rx_off_1 = 1'b0;
reg counter_at_tdd_tx_on_1 = 1'b0;
reg counter_at_tdd_tx_off_1 = 1'b0;
reg counter_at_tdd_tx_dp_on_1 = 1'b0;
reg counter_at_tdd_tx_dp_off_1 = 1'b0;
reg counter_at_tdd_vco_rx_on_2 = 1'b0;
reg counter_at_tdd_vco_rx_off_2 = 1'b0;
reg counter_at_tdd_vco_tx_on_2 = 1'b0;
reg counter_at_tdd_vco_tx_off_2 = 1'b0;
reg counter_at_tdd_rx_on_2 = 1'b0;
reg counter_at_tdd_rx_off_2 = 1'b0;
reg counter_at_tdd_tx_on_2 = 1'b0;
reg counter_at_tdd_tx_off_2 = 1'b0;
reg counter_at_tdd_tx_dp_on_2 = 1'b0;
reg counter_at_tdd_tx_dp_off_2 = 1'b0;
// internal signals
wire [21:0] tdd_tx_dp_on_1_s;
wire [21:0] tdd_tx_dp_on_2_s;
wire [21:0] tdd_tx_dp_off_1_s;
wire [21:0] tdd_tx_dp_off_2_s;
assign tdd_counter_status = tdd_counter;
// ***************************************************************************
// all the control registers needs to be updated at the same time
// ***************************************************************************
always @(posedge clk) begin
if(rst == 1'b1) begin
tdd_secondary_d <= 1'h0;
tdd_start_d <= 1'h0;
tdd_counter_init_d <= 22'h0;
tdd_frame_length_d <= 22'h0;
tdd_burst_en_d <= 1'h0;
tdd_burst_count_d <= 5'h0;
tdd_infinite_burst_d <= 1'h0;
tdd_tx_dp_delay_d <= 8'h0;
tdd_vco_rx_on_1_d <= 22'h0;
tdd_vco_rx_on_1_d <= 22'h0;
tdd_vco_tx_on_1_d <= 22'h0;
tdd_vco_tx_off_1_d <= 22'h0;
tdd_rx_on_1_d <= 22'h0;
tdd_rx_off_1_d <= 22'h0;
tdd_tx_on_1_d <= 22'h0;
tdd_tx_off_1_d <= 22'h0;
tdd_tx_dp_on_1_d <= 22'h0;
tdd_tx_dp_off_1_d <= 22'h0;
tdd_vco_rx_on_2_d <= 22'h0;
tdd_vco_rx_off_2_d <= 22'h0;
tdd_vco_tx_on_2_d <= 22'h0;
tdd_vco_tx_off_2_d <= 22'h0;
tdd_rx_on_2_d <= 22'h0;
tdd_rx_off_2_d <= 22'h0;
tdd_tx_on_2_d <= 22'h0;
tdd_tx_off_2_d <= 22'h0;
tdd_tx_dp_on_2_d <= 22'h0;
tdd_tx_dp_off_2_d <= 22'h0;
end else begin
//if((tdd_update_regs == 1'b1) && (tdd_counter_state == OFF)) begin
tdd_secondary_d <= tdd_secondary;
tdd_start_d <= tdd_start;
tdd_frame_length_d <= tdd_frame_length;
tdd_counter_init_d <= tdd_counter_init;
tdd_burst_en_d <= tdd_burst_en;
tdd_burst_count_d <= tdd_burst_count;
tdd_infinite_burst_d <= tdd_infinite_burst;
tdd_tx_dp_delay_d <= tdd_tx_dp_delay;
tdd_vco_rx_on_1_d <= tdd_vco_rx_on_1;
tdd_vco_rx_off_1_d <= tdd_vco_rx_off_1;
tdd_vco_tx_on_1_d <= tdd_vco_tx_on_1;
tdd_vco_tx_off_1_d <= tdd_vco_tx_off_1;
tdd_rx_on_1_d <= tdd_rx_on_1;
tdd_rx_off_1_d <= tdd_rx_off_1;
tdd_tx_on_1_d <= tdd_tx_on_1;
tdd_tx_off_1_d <= tdd_tx_off_1;
tdd_tx_dp_on_1_d <= tdd_tx_dp_on_1;
tdd_tx_dp_off_1_d <= tdd_tx_dp_off_1;
tdd_vco_rx_on_2_d <= tdd_vco_rx_on_2;
tdd_vco_rx_off_2_d <= tdd_vco_rx_off_2;
tdd_vco_tx_on_2_d <= tdd_vco_tx_on_2;
tdd_vco_tx_off_2_d <= tdd_vco_tx_off_2;
tdd_rx_on_2_d <= tdd_rx_on_2;
tdd_rx_off_2_d <= tdd_rx_off_2;
tdd_tx_on_2_d <= tdd_tx_on_2;
tdd_tx_off_2_d <= tdd_tx_off_2;
tdd_tx_dp_on_2_d <= tdd_tx_dp_on_2;
tdd_tx_dp_off_2_d <= tdd_tx_dp_off_2;
//end
end
end
// ***************************************************************************
// tdd counter (state machine)
// ***************************************************************************
@ -281,46 +202,44 @@ module ad_tdd_control(
if (rst == 1'b1) begin
tdd_counter <= 24'h0;
tdd_counter_state <= OFF;
tdd_burst_state <= OFF;
end else begin
// counter reset
if (tdd_counter_reset == 1'b1) begin
tdd_counter_state <= OFF;
tdd_burst_state <= OFF;
end else
// start counter, the start pulse should have one clock cycle
// NOTE: a start pulse during a transaction will reinitialize the counter
if (tdd_start == 1'b1) begin
tdd_counter <= tdd_counter_init_d;
tdd_burst_counter <= tdd_burst_count_d;
tdd_counter <= tdd_counter_init;
tdd_burst_counter <= tdd_burst_count;
tdd_counter_state <= ON;
if ((tdd_burst_en_d == 1) &&
((tdd_burst_count_d > 0) || (tdd_infinite_burst_d == 1))) begin
tdd_burst_state <= ON;
end else begin
tdd_burst_state <= OFF;
end
end else
// free running counter
if (tdd_counter_state == ON) begin
if (tdd_counter == tdd_frame_length_d) begin
if (tdd_counter == tdd_frame_length) begin
tdd_counter <= 22'h0;
if ((tdd_burst_state == ON) && ((tdd_burst_counter > 0) || (tdd_infinite_burst_d == 1))) begin
tdd_burst_counter <= tdd_burst_counter - 1;
tdd_counter_state <= ON;
end else begin
tdd_burst_counter <= 6'h0;
tdd_counter_state <= OFF;
tdd_burst_state <= OFF;
if (tdd_burst_en == 1) begin
if ( tdd_burst_counter > 0) begin // inside a burst
tdd_burst_counter <= tdd_burst_counter - 1;
tdd_counter_state <= ON;
end
else begin // end of burst
tdd_burst_counter <= 6'h0;
tdd_counter_state <= OFF;
end
end
end else begin
else begin // contiuous mode
tdd_burst_counter <= 6'h0;
tdd_counter_state <= ON;
end
end
else begin
tdd_counter <= tdd_counter + 1;
end
end
end
end
@ -329,15 +248,248 @@ module ad_tdd_control(
// ***************************************************************************
// start/stop rx vco
always @(posedge clk) begin
if(tdd_counter == tdd_vco_rx_on_1) begin
counter_at_tdd_vco_rx_on_1 <= 1'b1;
end
else begin
counter_at_tdd_vco_rx_on_1 <= 1'b0;
end
end
always @(posedge clk) begin
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_rx_on_2)) begin
counter_at_tdd_vco_rx_on_2 <= 1'b1;
end
else begin
counter_at_tdd_vco_rx_on_2 <= 1'b0;
end
end
always @(posedge clk) begin
if(tdd_counter == tdd_vco_rx_off_1) begin
counter_at_tdd_vco_rx_off_1 <= 1'b1;
end
else begin
counter_at_tdd_vco_rx_off_1 <= 1'b0;
end
end
always @(posedge clk) begin
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_rx_off_2)) begin
counter_at_tdd_vco_rx_off_2 <= 1'b1;
end
else begin
counter_at_tdd_vco_rx_off_2 <= 1'b0;
end
end
// start/stop tx vco
always @(posedge clk) begin
if(tdd_counter == tdd_vco_tx_on_1) begin
counter_at_tdd_vco_tx_on_1 <= 1'b1;
end
else begin
counter_at_tdd_vco_tx_on_1 <= 1'b0;
end
end
always @(posedge clk) begin
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_tx_on_2)) begin
counter_at_tdd_vco_tx_on_2 <= 1'b1;
end
else begin
counter_at_tdd_vco_tx_on_2 <= 1'b0;
end
end
always @(posedge clk) begin
if(tdd_counter == tdd_vco_tx_off_1) begin
counter_at_tdd_vco_tx_off_1 <= 1'b1;
end
else begin
counter_at_tdd_vco_tx_off_1 <= 1'b0;
end
end
always @(posedge clk) begin
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_tx_off_2)) begin
counter_at_tdd_vco_tx_off_2 <= 1'b1;
end
else begin
counter_at_tdd_vco_tx_off_2 <= 1'b0;
end
end
// start/stop rx rf path
always @(posedge clk) begin
if(tdd_counter == tdd_rx_on_1) begin
counter_at_tdd_rx_on_1 <= 1'b1;
end
else begin
counter_at_tdd_rx_on_1 <= 1'b0;
end
end
always @(posedge clk) begin
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_on_2)) begin
counter_at_tdd_rx_on_2 <= 1'b1;
end
else begin
counter_at_tdd_rx_on_2 <= 1'b0;
end
end
always @(posedge clk) begin
if(tdd_counter == tdd_rx_off_1) begin
counter_at_tdd_rx_off_1 <= 1'b1;
end
else begin
counter_at_tdd_rx_off_1 <= 1'b0;
end
end
always @(posedge clk) begin
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_off_2)) begin
counter_at_tdd_rx_off_2 <= 1'b1;
end
else begin
counter_at_tdd_rx_off_2 <= 1'b0;
end
end
// start/stop tx rf path
always @(posedge clk) begin
if(tdd_counter == tdd_tx_on_1) begin
counter_at_tdd_tx_on_1 <= 1'b1;
end
else begin
counter_at_tdd_tx_on_1 <= 1'b0;
end
end
always @(posedge clk) begin
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_on_2)) begin
counter_at_tdd_tx_on_2 <= 1'b1;
end
else begin
counter_at_tdd_tx_on_2 <= 1'b0;
end
end
always @(posedge clk) begin
if(tdd_counter == tdd_tx_off_1) begin
counter_at_tdd_tx_off_1 <= 1'b1;
end
else begin
counter_at_tdd_tx_off_1 <= 1'b0;
end
end
always @(posedge clk) begin
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_off_2)) begin
counter_at_tdd_tx_off_2 <= 1'b1;
end
else begin
counter_at_tdd_tx_off_2 <= 1'b0;
end
end
// start/stop tx data path
always @(posedge clk) begin
if(tdd_counter == tdd_tx_dp_on_1_s) begin
counter_at_tdd_tx_dp_on_1 <= 1'b1;
end
else begin
counter_at_tdd_tx_dp_on_1 <= 1'b0;
end
end
always @(posedge clk) begin
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_dp_on_2_s)) begin
counter_at_tdd_tx_dp_on_2 <= 1'b1;
end
else begin
counter_at_tdd_tx_dp_on_2 <= 1'b0;
end
end
always @(posedge clk) begin
if(tdd_counter == tdd_tx_dp_off_1_s) begin
counter_at_tdd_tx_dp_off_1 <= 1'b1;
end
else begin
counter_at_tdd_tx_dp_off_1 <= 1'b0;
end
end
always @(posedge clk) begin
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_dp_off_2_s)) begin
counter_at_tdd_tx_dp_off_2 <= 1'b1;
end
else begin
counter_at_tdd_tx_dp_off_2 <= 1'b0;
end
end
// internal datapath delay compensation
ad_addsub #(
.A_WIDTH(22),
.CONST_VALUE(11),
.ADD_SUB(1)
) i_tx_dp_on_1_comp (
.clk(clk),
.A(tdd_tx_dp_on_1),
.overflow(tdd_frame_length),
.out(tdd_tx_dp_on_1_s),
.CE(1)
);
ad_addsub #(
.A_WIDTH(22),
.CONST_VALUE(11),
.ADD_SUB(1)
) i_tx_dp_on_2_comp (
.clk(clk),
.A(tdd_tx_dp_on_2),
.overflow(tdd_frame_length),
.out(tdd_tx_dp_on_2_s),
.CE(1)
);
ad_addsub #(
.A_WIDTH(22),
.CONST_VALUE(11),
.ADD_SUB(1)
) i_tx_dp_off_1_comp (
.clk(clk),
.A(tdd_tx_dp_off_1),
.overflow(tdd_frame_length),
.out(tdd_tx_dp_off_1_s),
.CE(1)
);
ad_addsub #(
.A_WIDTH(22),
.CONST_VALUE(11),
.ADD_SUB(1)
) i_tx_dp_off_2_comp (
.clk(clk),
.A(tdd_tx_dp_off_2),
.overflow(tdd_frame_length),
.out(tdd_tx_dp_off_2_s),
.CE(1)
);
// output logic
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (tdd_counter == (tdd_vco_rx_on_1_d - 1)) begin
if (counter_at_tdd_vco_rx_on_1 || counter_at_tdd_vco_rx_on_2) begin
tdd_rx_vco_en <= 1'b1;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_vco_rx_on_2_d - 1))) begin
tdd_rx_vco_en <= 1'b1;
end else if (tdd_counter == (tdd_vco_rx_off_1_d - 1)) begin
tdd_rx_vco_en <= 1'b0;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_vco_rx_off_2_d - 1))) begin
end
else if (counter_at_tdd_vco_rx_off_1 || counter_at_tdd_vco_rx_off_2) begin
tdd_rx_vco_en <= 1'b0;
end
end else begin
@ -345,16 +497,12 @@ module ad_tdd_control(
end
end
// start/stop tx vco
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (tdd_counter == (tdd_vco_tx_on_1_d - 1)) begin
if (counter_at_tdd_vco_tx_on_1 || counter_at_tdd_vco_tx_on_2) begin
tdd_tx_vco_en <= 1'b1;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_vco_tx_on_2_d - 1))) begin
tdd_tx_vco_en <= 1'b1;
end else if (tdd_counter == (tdd_vco_tx_off_1_d - 1)) begin
tdd_tx_vco_en <= 1'b0;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_vco_tx_off_2_d - 1))) begin
end
else if (counter_at_tdd_vco_tx_off_1 || counter_at_tdd_vco_tx_off_2) begin
tdd_tx_vco_en <= 1'b0;
end
end else begin
@ -362,16 +510,12 @@ module ad_tdd_control(
end
end
// start/stop rx rf path
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (tdd_counter == (tdd_rx_on_1_d - 1)) begin
if (counter_at_tdd_rx_on_1 || counter_at_tdd_rx_on_2) begin
tdd_rx_rf_en <= 1'b1;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_rx_on_2_d - 1))) begin
tdd_rx_rf_en <= 1'b1;
end else if (tdd_counter == (tdd_rx_off_1_d - 1)) begin
tdd_rx_rf_en <= 1'b0;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_rx_off_2_d - 1))) begin
end
else if (counter_at_tdd_rx_off_1 || counter_at_tdd_rx_off_2) begin
tdd_rx_rf_en <= 1'b0;
end
end else begin
@ -379,16 +523,12 @@ module ad_tdd_control(
end
end
// start/stop tx rf path
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (tdd_counter == (tdd_tx_on_1_d - 1)) begin
if (counter_at_tdd_tx_on_1 || counter_at_tdd_tx_on_2) begin
tdd_tx_rf_en <= 1'b1;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_tx_on_2_d - 1))) begin
tdd_tx_rf_en <= 1'b1;
end else if (tdd_counter == (tdd_tx_off_1_d - 1)) begin
tdd_tx_rf_en <= 1'b0;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_tx_off_2_d - 1))) begin
end
else if (counter_at_tdd_tx_off_1 || counter_at_tdd_tx_off_2) begin
tdd_tx_rf_en <= 1'b0;
end
end else begin
@ -396,16 +536,12 @@ module ad_tdd_control(
end
end
// start/stop tx data path
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (tdd_counter == (tdd_tx_dp_on_1_d - tdd_tx_dp_delay_d)) begin
if (counter_at_tdd_tx_dp_on_1 || counter_at_tdd_tx_dp_on_2) begin
tdd_tx_dp_en <= 1'b1;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_tx_dp_on_2_d - tdd_tx_dp_delay_d))) begin
tdd_tx_dp_en <= 1'b1;
end else if (tdd_counter == (tdd_tx_dp_off_1_d - tdd_tx_dp_delay_d)) begin
tdd_tx_dp_en <= 1'b0;
end else if ((tdd_secondary_d == 1'b1) && (tdd_counter == (tdd_tx_dp_off_2_d - tdd_tx_dp_delay_d))) begin
end
else if (counter_at_tdd_tx_dp_off_1 || counter_at_tdd_tx_dp_off_2) begin
tdd_tx_dp_en <= 1'b0;
end
end else begin

33
library/common/up_tdd_cntrl.v
View File

@ -48,11 +48,9 @@ module up_tdd_cntrl (
tdd_start,
tdd_rst,
tdd_counter_reset,
tdd_update_regs,
tdd_secondary,
tdd_burst_en,
tdd_burst_count,
tdd_infinite_burst,
tdd_counter_init,
tdd_frame_length,
tdd_tx_dp_delay,
@ -102,7 +100,6 @@ module up_tdd_cntrl (
output tdd_enable;
output tdd_start;
output tdd_rst;
output tdd_update_regs;
output tdd_counter_reset;
output tdd_secondary;
output [21:0] tdd_counter_init;
@ -110,7 +107,6 @@ module up_tdd_cntrl (
output tdd_burst_en;
output [ 5:0] tdd_burst_count;
output tdd_infinite_burst;
output [ 7:0] tdd_tx_dp_delay;
output [21:0] tdd_vco_rx_on_1;
@ -159,7 +155,6 @@ module up_tdd_cntrl (
reg up_tdd_enable = 1'h0;
reg up_tdd_start = 1'h0;
reg up_tdd_update_regs = 1'h0;
reg up_tdd_counter_reset = 1'h0;
reg up_tdd_secondary = 1'h0;
reg [21:0] up_tdd_counter_init = 22'h0;
@ -167,7 +162,6 @@ module up_tdd_cntrl (
reg up_tdd_burst_en = 1'h0;
reg [ 5:0] up_tdd_burst_count = 6'h0;
reg up_tdd_infinite_burst = 1'h0;
reg [ 7:0] up_tdd_tx_dp_delay = 8'h0;
reg [21:0] up_tdd_vco_rx2tx_1 = 22'h0;
@ -217,7 +211,6 @@ module up_tdd_cntrl (
up_scratch <= 32'h0;
up_resetn <= 1'h0;
up_tdd_start <= 1'h0;
up_tdd_update_regs <= 1'h0;
up_tdd_counter_reset <= 1'h0;
up_tdd_enable <= 1'h0;
up_tdd_secondary <= 1'h0;
@ -225,7 +218,6 @@ module up_tdd_cntrl (
up_tdd_frame_length <= 22'h0;
up_tdd_burst_en <= 1'h0;
up_tdd_burst_count <= 6'h0;
up_tdd_infinite_burst <= 1'h0;
up_tdd_vco_rx_on_1 <= 22'h0;
up_tdd_vco_rx_off_1 <= 22'h0;
up_tdd_vco_tx_on_1 <= 22'h0;
@ -252,25 +244,20 @@ module up_tdd_cntrl (
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_resetn <= up_wdata[0];
end
if (up_tdd_update_regs == 1'b1) begin
if (up_cntrl_xfer_done == 1) begin
up_tdd_update_regs <= 1'h0;
end
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_tdd_update_regs <= up_wdata[3];
up_tdd_counter_reset <= up_wdata[2];
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_tdd_enable <= up_wdata[0];
end
if (up_tdd_start == 1) begin
if (up_cntrl_xfer_done == 1) begin
up_tdd_start <= 1'h0;
up_tdd_counter_reset <= 1'h0;
end
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_tdd_counter_reset <= up_wdata[2];
up_tdd_start <= up_wdata[1];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
up_tdd_burst_count <= up_wdata[21:16];
up_tdd_infinite_burst <= up_wdata[2];
up_tdd_burst_en <= up_wdata[1];
up_tdd_secondary <= up_wdata[0];
end
@ -360,8 +347,8 @@ module up_tdd_cntrl (
8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {31'h0, up_resetn};
8'h11: up_rdata <= {28'h0, up_tdd_update_regs, up_tdd_counter_reset, up_tdd_start, up_tdd_enable};
8'h12: up_rdata <= {10'h0, up_tdd_burst_count, 13'h0, up_tdd_infinite_burst, up_tdd_burst_en, up_tdd_secondary};
8'h11: up_rdata <= {29'h0, up_tdd_counter_reset, up_tdd_start, up_tdd_enable};
8'h12: up_rdata <= {10'h0, up_tdd_burst_count, 14'h0, up_tdd_burst_en, up_tdd_secondary};
8'h13: up_rdata <= {10'h0, up_tdd_counter_init};
8'h14: up_rdata <= {10'h0, up_tdd_frame_length};
8'h15: up_rdata <= {24'h0, up_tdd_tx_dp_delay};
@ -402,29 +389,25 @@ module up_tdd_cntrl (
// rf tdd control signal CDC
up_xfer_cntrl #(.DATA_WIDTH(13)) i_tdd_control (
up_xfer_cntrl #(.DATA_WIDTH(11)) i_tdd_control (
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_cntrl({up_tdd_enable,
up_tdd_counter_reset,
up_tdd_update_regs,
up_tdd_secondary,
up_tdd_start,
up_tdd_burst_en,
up_tdd_burst_count,
up_tdd_infinite_burst
up_tdd_burst_count
}),
.up_xfer_done(up_cntrl_xfer_done),
.d_rst(tdd_rst),
.d_clk(clk),
.d_data_cntrl({tdd_enable,
tdd_counter_reset,
tdd_update_regs,
tdd_secondary,
tdd_start,
tdd_burst_en,
tdd_burst_count,
tdd_infinite_burst
tdd_burst_count
}));
up_xfer_cntrl #(.DATA_WIDTH(492)) i_tdd_counter_values (