axi_jesd204_rx: Added 64b mode

main
Laszlo Nagy 2019-10-10 08:22:02 +01:00 committed by Laszlo Nagy
parent d1072847df
commit 7cad1f81d9
5 changed files with 61 additions and 21 deletions

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@ -47,7 +47,8 @@
module axi_jesd204_rx #( module axi_jesd204_rx #(
parameter ID = 0, parameter ID = 0,
parameter NUM_LANES = 1, parameter NUM_LANES = 1,
parameter NUM_LINKS = 1 parameter NUM_LINKS = 1,
parameter LINK_MODE = 1 // 2 - 64B/66B; 1 - 8B/10B
) ( ) (
input s_axi_aclk, input s_axi_aclk,
input s_axi_aresetn, input s_axi_aresetn,
@ -97,13 +98,14 @@ module axi_jesd204_rx #(
input core_event_sysref_alignment_error, input core_event_sysref_alignment_error,
input core_event_sysref_edge, input core_event_sysref_edge,
output [2:0] core_ctrl_err_statistics_mask, output [6:0] core_ctrl_err_statistics_mask,
output core_ctrl_err_statistics_reset, output core_ctrl_err_statistics_reset,
input [32*NUM_LANES-1:0] core_status_err_statistics_cnt, input [32*NUM_LANES-1:0] core_status_err_statistics_cnt,
input [1:0] core_status_ctrl_state, input [1:0] core_status_ctrl_state,
input [2*NUM_LANES-1:0] core_status_lane_cgs_state, input [2*NUM_LANES-1:0] core_status_lane_cgs_state,
input [3*NUM_LANES-1:0] core_status_lane_emb_state,
input [NUM_LANES-1:0] core_status_lane_ifs_ready, input [NUM_LANES-1:0] core_status_lane_ifs_ready,
input [14*NUM_LANES-1:0] core_status_lane_latency input [14*NUM_LANES-1:0] core_status_lane_latency
); );
@ -111,6 +113,8 @@ module axi_jesd204_rx #(
localparam PCORE_VERSION = 32'h00010261; // 1.02.a localparam PCORE_VERSION = 32'h00010261; // 1.02.a
localparam PCORE_MAGIC = 32'h32303452; // 204R localparam PCORE_MAGIC = 32'h32303452; // 204R
localparam DATA_PATH_WIDTH = LINK_MODE == 2 ? 3 : 2;
/* Register interface signals */ /* Register interface signals */
reg [31:0] up_rdata = 'h0; reg [31:0] up_rdata = 'h0;
reg up_wack = 1'b0; reg up_wack = 1'b0;
@ -175,9 +179,10 @@ jesd204_up_common #(
.ID(ID), .ID(ID),
.NUM_LANES(NUM_LANES), .NUM_LANES(NUM_LANES),
.NUM_LINKS(NUM_LINKS), .NUM_LINKS(NUM_LINKS),
.DATA_PATH_WIDTH(2), .DATA_PATH_WIDTH(DATA_PATH_WIDTH),
.NUM_IRQS(5), .NUM_IRQS(5),
.EXTRA_CFG_WIDTH(19) .EXTRA_CFG_WIDTH(19),
.LINK_MODE(LINK_MODE)
) i_up_common ( ) i_up_common (
.up_clk(s_axi_aclk), .up_clk(s_axi_aclk),
.ext_resetn(s_axi_aresetn), .ext_resetn(s_axi_aresetn),
@ -223,7 +228,9 @@ jesd204_up_common #(
}) })
); );
jesd204_up_sysref i_up_sysref ( jesd204_up_sysref #(
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
) i_up_sysref (
.up_clk(s_axi_aclk), .up_clk(s_axi_aclk),
.up_reset(up_reset), .up_reset(up_reset),
@ -245,7 +252,8 @@ jesd204_up_sysref i_up_sysref (
); );
jesd204_up_rx #( jesd204_up_rx #(
.NUM_LANES(NUM_LANES) .NUM_LANES(NUM_LANES),
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
) i_up_rx ( ) i_up_rx (
.up_clk(s_axi_aclk), .up_clk(s_axi_aclk),
.up_reset(up_reset), .up_reset(up_reset),
@ -271,6 +279,7 @@ jesd204_up_rx #(
.core_status_ctrl_state(core_status_ctrl_state), .core_status_ctrl_state(core_status_ctrl_state),
.core_status_lane_cgs_state(core_status_lane_cgs_state), .core_status_lane_cgs_state(core_status_lane_cgs_state),
.core_status_lane_emb_state(core_status_lane_emb_state),
.core_status_lane_ifs_ready(core_status_lane_ifs_ready), .core_status_lane_ifs_ready(core_status_lane_ifs_ready),
.core_status_lane_latency(core_status_lane_latency), .core_status_lane_latency(core_status_lane_latency),

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@ -108,7 +108,8 @@ set_false_path \
-from $core_clk \ -from $core_clk \
-to [get_pins {i_up_rx/*i_up_rx_lane/i_ilas_mem/i_cdc_ilas_ready/cdc_sync_stage1_reg[0]/D}] -to [get_pins {i_up_rx/*i_up_rx_lane/i_ilas_mem/i_cdc_ilas_ready/cdc_sync_stage1_reg[0]/D}]
set_max_delay -datapath_only \ # Use -quiet here since the ILAS mem is missing in non 8b10b configuration
set_max_delay -quiet -datapath_only \
-from [get_pins {i_up_rx/gen_lane[*].i_up_rx_lane/i_ilas_mem/mem_reg_*/*/CLK}] \ -from [get_pins {i_up_rx/gen_lane[*].i_up_rx_lane/i_ilas_mem/mem_reg_*/*/CLK}] \
-to [get_pins {i_up_rx/gen_lane[*].i_up_rx_lane/i_ilas_mem/up_rdata_reg[*]/D}] \ -to [get_pins {i_up_rx/gen_lane[*].i_up_rx_lane/i_ilas_mem/up_rdata_reg[*]/D}] \
[get_property -min PERIOD $axi_clk] [get_property -min PERIOD $axi_clk]

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@ -68,8 +68,8 @@ adi_ip_add_core_dependencies { \
analog.com:user:axi_jesd204_common:1.0 \ analog.com:user:axi_jesd204_common:1.0 \
} }
set_property display_name "ADI JESD204B Receive AXI Interface" [ipx::current_core] set_property display_name "ADI JESD204C Receive AXI Interface" [ipx::current_core]
set_property description "ADI JESD204B Receive AXI Interface" [ipx::current_core] set_property description "ADI JESD204C Receive AXI Interface" [ipx::current_core]
adi_add_bus "rx_cfg" "master" \ adi_add_bus "rx_cfg" "master" \
"analog.com:interface:jesd204_rx_cfg_rtl:1.0" \ "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \
@ -113,6 +113,7 @@ adi_add_bus "rx_status" "slave" \
{ \ { \
{ "core_status_ctrl_state" "ctrl_state" } \ { "core_status_ctrl_state" "ctrl_state" } \
{ "core_status_lane_cgs_state" "lane_cgs_state" } \ { "core_status_lane_cgs_state" "lane_cgs_state" } \
{ "core_status_lane_emb_state" "lane_emb_state" } \
{ "core_status_lane_ifs_ready" "lane_ifs_ready" } \ { "core_status_lane_ifs_ready" "lane_ifs_ready" } \
{ "core_status_lane_latency" "lane_latency" } \ { "core_status_lane_latency" "lane_latency" } \
{ "core_status_err_statistics_cnt" "err_statistics_cnt" } \ { "core_status_err_statistics_cnt" "err_statistics_cnt" } \
@ -125,4 +126,24 @@ adi_add_bus_clock "core_clk" "rx_status:rx_event:rx_ilas_config:rx_cfg" \
set_property DRIVER_VALUE "0" [ipx::get_ports "core_reset_ext"] set_property DRIVER_VALUE "0" [ipx::get_ports "core_reset_ext"]
adi_set_bus_dependency "rx_ilas_config" "rx_ilas_config" \
"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
set cc [ipx::current_core]
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
# Link layer mode
set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $page0
set_property -dict [list \
"display_name" "Link Layer mode" \
"tooltip" "Link Layer mode" \
"widget" "comboBox" \
] $p
set_property -dict [list \
value_validation_type pairs \
value_validation_pairs {64B66B 2 8B10B 1} \
] [ipx::get_user_parameters $p -of_objects $cc]
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

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@ -45,7 +45,8 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module jesd204_up_rx # ( module jesd204_up_rx # (
parameter NUM_LANES = 1 parameter NUM_LANES = 1,
parameter DATA_PATH_WIDTH = 2
) ( ) (
input up_clk, input up_clk,
input up_reset, input up_reset,
@ -67,11 +68,12 @@ module jesd204_up_rx # (
input [1:0] core_status_ctrl_state, input [1:0] core_status_ctrl_state,
input [2*NUM_LANES-1:0] core_status_lane_cgs_state, input [2*NUM_LANES-1:0] core_status_lane_cgs_state,
input [3*NUM_LANES-1:0] core_status_lane_emb_state,
input [NUM_LANES-1:0] core_status_lane_ifs_ready, input [NUM_LANES-1:0] core_status_lane_ifs_ready,
input [14*NUM_LANES-1:0] core_status_lane_latency, input [14*NUM_LANES-1:0] core_status_lane_latency,
input [32*NUM_LANES-1:0] core_status_err_statistics_cnt, input [32*NUM_LANES-1:0] core_status_err_statistics_cnt,
output [2:0] core_ctrl_err_statistics_mask, output [6:0] core_ctrl_err_statistics_mask,
output core_ctrl_err_statistics_reset, output core_ctrl_err_statistics_reset,
input up_cfg_is_writeable, input up_cfg_is_writeable,
@ -83,31 +85,34 @@ localparam ELASTIC_BUFFER_SIZE = 256;
wire [1:0] up_status_ctrl_state; wire [1:0] up_status_ctrl_state;
wire [2*NUM_LANES-1:0] up_status_lane_cgs_state; wire [2*NUM_LANES-1:0] up_status_lane_cgs_state;
wire [3*NUM_LANES-1:0] up_status_lane_emb_state;
wire [31:0] up_lane_rdata[0:NUM_LANES-1]; wire [31:0] up_lane_rdata[0:NUM_LANES-1];
wire [32*NUM_LANES-1:0] up_status_err_statistics_cnt; wire [32*NUM_LANES-1:0] up_status_err_statistics_cnt;
reg up_ctrl_err_statistics_reset = 0; reg up_ctrl_err_statistics_reset = 0;
reg [2:0] up_ctrl_err_statistics_mask = 3'h0; reg [6:0] up_ctrl_err_statistics_mask = 7'h0;
sync_data #( sync_data #(
.NUM_OF_BITS(2+NUM_LANES*(2+32)) .NUM_OF_BITS(2+NUM_LANES*(3+2+32))
) i_cdc_status ( ) i_cdc_status (
.in_clk(core_clk), .in_clk(core_clk),
.in_data({ .in_data({
core_status_err_statistics_cnt, core_status_err_statistics_cnt,
core_status_ctrl_state, core_status_ctrl_state,
core_status_lane_cgs_state core_status_lane_cgs_state,
core_status_lane_emb_state
}), }),
.out_clk(up_clk), .out_clk(up_clk),
.out_data({ .out_data({
up_status_err_statistics_cnt, up_status_err_statistics_cnt,
up_status_ctrl_state, up_status_ctrl_state,
up_status_lane_cgs_state up_status_lane_cgs_state,
up_status_lane_emb_state
}) })
); );
sync_data #( sync_data #(
.NUM_OF_BITS(4) .NUM_OF_BITS(8)
) i_cdc_cfg ( ) i_cdc_cfg (
.in_clk(up_clk), .in_clk(up_clk),
.in_data({ .in_data({
@ -137,8 +142,8 @@ always @(*) begin
/* 00-01 */ 2'b00 /* Data path width alignment */ /* 00-01 */ 2'b00 /* Data path width alignment */
}; };
12'h91: up_rdata <= { 12'h91: up_rdata <= {
/* 11-31 */ 21'h00, /* Reserved for future additions */ /* 15-31 */ 17'h00, /* Reserved for future additions */
/* 08-10 */ up_ctrl_err_statistics_mask, /* 08-14 */ up_ctrl_err_statistics_mask,
/* 01-07 */ 7'h0, /* 01-07 */ 7'h0,
/* 00 */ up_ctrl_err_statistics_reset /* 00 */ up_ctrl_err_statistics_reset
}; };
@ -165,20 +170,20 @@ always @(posedge up_clk) begin
if (up_reset == 1'b1) begin if (up_reset == 1'b1) begin
up_cfg_buffer_early_release <= 1'b0; up_cfg_buffer_early_release <= 1'b0;
up_cfg_buffer_delay <= 'h00; up_cfg_buffer_delay <= 'h00;
up_ctrl_err_statistics_mask <= 3'h0; up_ctrl_err_statistics_mask <= 7'h0;
up_ctrl_err_statistics_reset <= 1'b0; up_ctrl_err_statistics_reset <= 1'b0;
end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
case (up_waddr) case (up_waddr)
/* JESD RX configuraton */ /* JESD RX configuraton */
12'h090: begin 12'h090: begin
up_cfg_buffer_early_release <= up_wdata[16]; up_cfg_buffer_early_release <= up_wdata[16];
up_cfg_buffer_delay <= up_wdata[9:2]; up_cfg_buffer_delay <= up_wdata[9:DATA_PATH_WIDTH];
end end
endcase endcase
end else if (up_wreq == 1'b1) begin end else if (up_wreq == 1'b1) begin
case (up_waddr) case (up_waddr)
12'h91: begin 12'h91: begin
up_ctrl_err_statistics_mask <= up_wdata[10:8]; up_ctrl_err_statistics_mask <= up_wdata[14:8];
up_ctrl_err_statistics_reset <= up_wdata[0]; up_ctrl_err_statistics_reset <= up_wdata[0];
end end
endcase endcase
@ -197,6 +202,7 @@ generate for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
.up_status_cgs_state(up_status_lane_cgs_state[2*i+1:2*i]), .up_status_cgs_state(up_status_lane_cgs_state[2*i+1:2*i]),
.up_status_err_statistics_cnt(up_status_err_statistics_cnt[32*i+31:32*i]), .up_status_err_statistics_cnt(up_status_err_statistics_cnt[32*i+31:32*i]),
.up_status_emb_state(up_status_lane_emb_state[3*i+2:3*i]),
.core_clk(core_clk), .core_clk(core_clk),
.core_reset(core_reset), .core_reset(core_reset),

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@ -54,6 +54,7 @@ module jesd204_up_rx_lane (
input [1:0] up_status_cgs_state, input [1:0] up_status_cgs_state,
input [31:0] up_status_err_statistics_cnt, input [31:0] up_status_err_statistics_cnt,
input [2:0] up_status_emb_state,
input core_clk, input core_clk,
input core_reset, input core_reset,
@ -108,6 +109,8 @@ always @(*) begin
case (up_raddr[1:0]) case (up_raddr[1:0])
2'b00: up_rdata <= { 2'b00: up_rdata <= {
/* 06-31 */ 26'h00, /* Reserved for future use */ /* 06-31 */ 26'h00, /* Reserved for future use */
/* 08-10 */ up_status_emb_state,
/* 06-07 */ 2'h00,
/* 05 */ up_ilas_ready, /* 05 */ up_ilas_ready,
/* 04 */ up_status_ifs_ready, /* 04 */ up_status_ifs_ready,
/* 02-03 */ 2'b00, /* Reserved for future extensions of cgs_state */ /* 02-03 */ 2'b00, /* Reserved for future extensions of cgs_state */