From 7da98277821dff950871b3a8cafa6b2b789da7ed Mon Sep 17 00:00:00 2001 From: alin724 Date: Wed, 29 Mar 2023 14:57:06 +0300 Subject: [PATCH] ad7606x_fmc: Fix up_cpack2 module's SAMPLE_DATA_WIDTH parameter --- projects/ad7606x_fmc/common/ad7606x_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/ad7606x_fmc/common/ad7606x_bd.tcl b/projects/ad7606x_fmc/common/ad7606x_bd.tcl index 2e89685e2..b677a9723 100644 --- a/projects/ad7606x_fmc/common/ad7606x_bd.tcl +++ b/projects/ad7606x_fmc/common/ad7606x_bd.tcl @@ -56,7 +56,7 @@ ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_DATA_WIDTH_DEST 64 ad_ip_instance util_cpack2 ad7606x_adc_pack ad_ip_parameter ad7606x_adc_pack CONFIG.NUM_OF_CHANNELS 8 -ad_ip_parameter ad7606x_adc_pack CONFIG.SAMPLE_DATA_WIDTH $ADC_N_BITS +ad_ip_parameter ad7606x_adc_pack CONFIG.SAMPLE_DATA_WIDTH $ADC_TO_DMA_N_BITS if {$EXT_CLK == 1} { # use Xilinx's clocking wizard in order to generate th clock from the CPU clock, this being then assigned to the adc_clk in the axi_ad7606x IP