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ad7606x_fmc: Fix up_cpack2 module's SAMPLE_DATA_WIDTH parameter

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alin724 2023-03-29 14:57:06 +03:00 committed by Alin-Tudor Sferle
parent f945520020
commit 7da9827782
1 changed files with 1 additions and 1 deletions
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projects/ad7606x_fmc/common/ad7606x_bd.tcl
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@ -56,7 +56,7 @@ ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_ip_instance util_cpack2 ad7606x_adc_pack
ad_ip_parameter ad7606x_adc_pack CONFIG.NUM_OF_CHANNELS 8
ad_ip_parameter ad7606x_adc_pack CONFIG.SAMPLE_DATA_WIDTH $ADC_N_BITS
ad_ip_parameter ad7606x_adc_pack CONFIG.SAMPLE_DATA_WIDTH $ADC_TO_DMA_N_BITS
if {$EXT_CLK == 1} {
# use Xilinx's clocking wizard in order to generate th clock from the CPU clock, this being then assigned to the adc_clk in the axi_ad7606x IP