util_upack: Fixed ip
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8542c2b0d7
commit
7e15fd9e5b
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@ -176,11 +176,11 @@ module util_upack (
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generate
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if (P_CNT < M_CNT) begin
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for (n = P_CNT; n < M_CNT; n = n + 1) begin: g_def
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assign dac_dsf_valid_s[n] = 'd0;
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assign dac_dsf_sync_s[n] = 'd0;
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assign dac_dsf_data_s[n] = 'd0;
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end
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for (n = P_CNT; n < M_CNT; n = n + 1) begin: g_def
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assign dac_dsf_valid_s[n] = 'd0;
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assign dac_dsf_sync_s[n] = 'd0;
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assign dac_dsf_data_s[n] = 'd0;
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end
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end
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for (n = 0; n < P_CNT; n = n + 1) begin: g_dsf
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@ -102,6 +102,16 @@ module util_upack_dsf (
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// bypass
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genvar i;
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generate
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if (CH_OCNT == P_CNT) begin
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for (i = 0; i < CH_SCNT ; i = i +1) begin
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assign dac_dsf_data_s[(((i +1) * M_CNT * 16)-1):(i*M_CNT*16)] =
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dac_data[(((i+1)*16*P_CNT)-1): (i*16*P_CNT)];
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end
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end
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endgenerate
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generate
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if (CH_OCNT == P_CNT) begin
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@ -109,8 +119,6 @@ module util_upack_dsf (
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assign dac_data_s = 'd0;
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assign dac_data_int_0_s = 'd0;
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assign dac_data_int_1_s = 'd0;
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assign dac_dsf_data_s[M_WIDTH:P_WIDTH] = 'd0;
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assign dac_dsf_data_s[(P_WIDTH-1):0] = dac_data;
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always @(posedge dac_clk) begin
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dac_dmx_valid <= dac_valid & dac_dmx_enable;
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@ -165,7 +173,7 @@ module util_upack_dsf (
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dac_data_int[(M_WIDTH-1):(M_WIDTH-(E_WIDTH-P_WIDTH))];
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assign dac_data_int_1_s[(E_WIDTH-1):(E_WIDTH-(M_WIDTH-O_WIDTH))] =
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dac_data_int[((M_WIDTH-O_WIDTH)-1):0];
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dac_data_int[(M_WIDTH-1):O_WIDTH];
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assign dac_data_int_1_s[((E_WIDTH-(M_WIDTH-O_WIDTH))-1):0] = 'd0;
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always @(posedge dac_clk) begin
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