adrv9371:a10gx: Remove constraint from DDR
parent
359e5d94ec
commit
7e22f91429
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@ -8,11 +8,6 @@ derive_clock_uncertainty
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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if {[string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)]} {
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set_max_delay -from [get_clocks *sys_ddr3_cntrl_phy_clk_l*] -to [get_clocks *sys_ddr3_cntrl_core_usr_clk*] 0.150
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set_min_delay -from [get_clocks *sys_ddr3_cntrl_phy_clk_l*] -to [get_clocks *sys_ddr3_cntrl_core_usr_clk*] 0.000
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}
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# flash interface
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# flash interface
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set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_addr[*]} ]
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set_output_delay -clock [ get_clocks sys_clk_100mhz ] 2 [ get_ports {flash_addr[*]} ]
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