zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fmcomms2: Improved constraints for ac701 and zc702. Fixed common design so that ILA works correctly on microblaze based systems

main
Adrian Costina 2014-09-22 14:40:11 -04:00
parent 577441bd0c
commit 7e40f99fe9
3 changed files with 21 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
projects/fmcomms2/ac701/system_constr.xdc
View File

@ -60,8 +60,8 @@ set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS25} [get_ports spi_miso]
# clocks
create_clock -name rx_clk -period 5 [get_ports rx_clk_in_p]
create_clock -name ad9361_clk -period 5 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p]
create_clock -name ad9361_clk -period 4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
set_clock_groups -asynchronous -group {ad9361_clk}

26
projects/fmcomms2/common/fmcomms2_bd.tcl
View File

@ -274,11 +274,11 @@ if {$sys_zynq == 0} {
# memory interconnects share the same clock (fclk2)
if {$sys_zynq == 1} {
set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
}
# interconnect (mem/dac)
if {$sys_zynq == 0} {
@ -339,19 +339,28 @@ if {$sys_zynq == 0} {
p_sys_wfifo [current_bd_instance .] sys_wfifo_2 16 16
p_sys_wfifo [current_bd_instance .] sys_wfifo_3 16 16
connect_bd_net -net axi_ad9361_clk [get_bd_pins sys_wfifo_0/m_clk] [get_bd_pins axi_ad9361/l_clk]
connect_bd_net -net axi_ad9361_clk [get_bd_pins sys_wfifo_1/m_clk] [get_bd_pins axi_ad9361/l_clk]
connect_bd_net -net axi_ad9361_clk [get_bd_pins sys_wfifo_2/m_clk] [get_bd_pins axi_ad9361/l_clk]
connect_bd_net -net axi_ad9361_clk [get_bd_pins sys_wfifo_3/m_clk] [get_bd_pins axi_ad9361/l_clk]
if {$sys_zynq == 0} {
connect_bd_net -net sys_200m_clk [get_bd_pins ila_adc/clk]
connect_bd_net -net sys_200m_clk [get_bd_pins sys_wfifo_0/s_clk] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins sys_wfifo_1/s_clk] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins sys_wfifo_2/s_clk] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins sys_wfifo_3/s_clk] $sys_200m_clk_source
} else {
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins ila_adc/clk]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_wfifo_0/s_clk] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_wfifo_1/s_clk] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_wfifo_2/s_clk] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_wfifo_3/s_clk] $sys_fmc_dma_clk_source
}
connect_bd_net -net axi_ad9361_clk [get_bd_pins sys_wfifo_0/m_clk] [get_bd_pins axi_ad9361/l_clk]
connect_bd_net -net axi_ad9361_clk [get_bd_pins sys_wfifo_1/m_clk] [get_bd_pins axi_ad9361/l_clk]
connect_bd_net -net axi_ad9361_clk [get_bd_pins sys_wfifo_2/m_clk] [get_bd_pins axi_ad9361/l_clk]
connect_bd_net -net axi_ad9361_clk [get_bd_pins sys_wfifo_3/m_clk] [get_bd_pins axi_ad9361/l_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins sys_wfifo_0/rstn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins sys_wfifo_1/rstn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins sys_wfifo_2/rstn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins sys_wfifo_3/rstn] $sys_100m_resetn_source
connect_bd_net -net axi_ad9361_adc_valid_i0 [get_bd_pins sys_wfifo_0/m_wr] [get_bd_pins axi_ad9361/adc_valid_i0]
connect_bd_net -net axi_ad9361_adc_valid_q0 [get_bd_pins sys_wfifo_1/m_wr] [get_bd_pins axi_ad9361/adc_valid_q0]
connect_bd_net -net axi_ad9361_adc_valid_i1 [get_bd_pins sys_wfifo_2/m_wr] [get_bd_pins axi_ad9361/adc_valid_i1]
@ -361,7 +370,6 @@ if {$sys_zynq == 0} {
connect_bd_net -net axi_ad9361_adc_chan_i1 [get_bd_pins sys_wfifo_2/m_wdata] [get_bd_pins axi_ad9361/adc_data_i1]
connect_bd_net -net axi_ad9361_adc_chan_q1 [get_bd_pins sys_wfifo_3/m_wdata] [get_bd_pins axi_ad9361/adc_data_q1]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins ila_adc/clk]
connect_bd_net -net util_wfifo_0_s_wr [get_bd_pins sys_wfifo_0/s_wr] [get_bd_pins ila_adc/probe0]
connect_bd_net -net util_wfifo_1_s_wr [get_bd_pins sys_wfifo_1/s_wr] [get_bd_pins ila_adc/probe1]
connect_bd_net -net util_wfifo_2_s_wr [get_bd_pins sys_wfifo_2/s_wr] [get_bd_pins ila_adc/probe2]

4
projects/fmcomms2/zc702/system_constr.xdc
View File

@ -60,8 +60,8 @@ set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25} [get_ports spi_miso]
# clocks
create_clock -name rx_clk -period 5 [get_ports rx_clk_in_p]
create_clock -name ad9361_clk -period 5 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p]
create_clock -name ad9361_clk -period 4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
create_clock -name fmc_dma_clk -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
set_clock_groups -asynchronous -group {ad9361_clk}