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common: a10soc: Mark external reset as asynchronous 

There is no guarantee that the external reset de-assertion is synchronous
to the sys_clk, yet the clock bridge marks the reset de-assertion as
synchronized to the clock. This can cause recovery or removal timing
violations for the registers affected by this reset signal and potentially
bring the system into an invalid state after the reset is de-asserted.

Mark the reset as not synchronized to the clock signal, this will make sure
that Qsys inserts the proper reset synchronizers where required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-08-03 17:17:15 +02:00
parent fa9d94bfe8
commit 7eba8326dd
1 changed files with 1 additions and 1 deletions
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projects/common/a10soc/a10soc_system_qsys.tcl
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@ -11,7 +11,7 @@ add_interface sys_rstn reset sink
set_interface_property sys_rstn EXPORT_OF sys_clk.clk_in_reset
set_instance_parameter_value sys_clk {clockFrequency} {100000000.0}
set_instance_parameter_value sys_clk {clockFrequencyKnown} {1}
set_instance_parameter_value sys_clk {resetSynchronousEdges} {DEASSERT}
set_instance_parameter_value sys_clk {resetSynchronousEdges} {NONE}
# hps
# round-about way - qsys-script doesn't support {*}?