From 7f377454a8509dcd555ef843cacb362b3d6bd408 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Wed, 28 Feb 2018 13:37:40 +0000 Subject: [PATCH] daq2/fmcadc4/daq3: Disable the transfer start sync on the ADC DMA Explicitly disable the "Transfer Start Synchronisation Support" since the sync lines are not connected in this project. If the sync input line (s_axi_user[0] or fifo_wr_sync) are not connected, Vivado 2017.4.1 no longer connects them to the defaultValue defined in the axi_dmac ip (1). Instead he uses the defaulValue field defined in the interface definition which in case of both interfaces is 0; --- projects/daq2/common/daq2_bd.tcl | 2 +- projects/daq3/common/daq3_bd.tcl | 2 +- projects/fmcadc4/common/fmcadc4_bd.tcl | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl index db8b8e95e..d5608866f 100644 --- a/projects/daq2/common/daq2_bd.tcl +++ b/projects/daq2/common/daq2_bd.tcl @@ -50,7 +50,7 @@ ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_DEST 0 ad_ip_parameter axi_ad9680_dma CONFIG.ID 0 ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_SRC 0 ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_DEST 0 -ad_ip_parameter axi_ad9680_dma CONFIG.SYNC_TRANSFER_START 1 +ad_ip_parameter axi_ad9680_dma CONFIG.SYNC_TRANSFER_START 0 ad_ip_parameter axi_ad9680_dma CONFIG.DMA_LENGTH_WIDTH 24 ad_ip_parameter axi_ad9680_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0 diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl index 5de8110da..5713976f8 100644 --- a/projects/daq3/common/daq3_bd.tcl +++ b/projects/daq3/common/daq3_bd.tcl @@ -49,7 +49,7 @@ ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_DEST 0 ad_ip_parameter axi_ad9680_dma CONFIG.ID 0 ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_SRC 0 ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_DEST 0 -ad_ip_parameter axi_ad9680_dma CONFIG.SYNC_TRANSFER_START 1 +ad_ip_parameter axi_ad9680_dma CONFIG.SYNC_TRANSFER_START 0 ad_ip_parameter axi_ad9680_dma CONFIG.DMA_LENGTH_WIDTH 24 ad_ip_parameter axi_ad9680_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0 diff --git a/projects/fmcadc4/common/fmcadc4_bd.tcl b/projects/fmcadc4/common/fmcadc4_bd.tcl index d3040673d..f6e58d16b 100644 --- a/projects/fmcadc4/common/fmcadc4_bd.tcl +++ b/projects/fmcadc4/common/fmcadc4_bd.tcl @@ -23,7 +23,7 @@ ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_DEST 0 ad_ip_parameter axi_ad9680_dma CONFIG.ID 0 ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_SRC 0 ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_DEST 0 -ad_ip_parameter axi_ad9680_dma CONFIG.SYNC_TRANSFER_START 1 +ad_ip_parameter axi_ad9680_dma CONFIG.SYNC_TRANSFER_START 0 ad_ip_parameter axi_ad9680_dma CONFIG.DMA_LENGTH_WIDTH 24 ad_ip_parameter axi_ad9680_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0