zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

axi_dmac: fix timing constraints 

When source clock is asynchronous to request clock the rewind request
handshake block must be constrained based on request clock domain.
main
Laszlo Nagy 2019-07-26 13:07:51 +01:00 committed by István Csomortáni
parent 6fad82c329
commit 7f72340be8
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
library/axi_dmac/axi_dmac_constr.ttcl
View File

@ -67,16 +67,16 @@ set_max_delay -quiet -datapath_only \
[get_property -min PERIOD $src_clk]
set_max_delay -quiet -datapath_only \
-from $dest_clk \
-from $req_clk \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_rewind_req_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \
[get_property -min PERIOD $dest_clk]
[get_property -min PERIOD $req_clk]
set_max_delay -quiet -datapath_only \
-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
-filter {NAME =~ *i_rewind_req_fifo* && IS_SEQUENTIAL}] \
-to $dest_clk \
[get_property -min PERIOD $dest_clk]
-to $req_clk \
[get_property -min PERIOD $req_clk]
set_false_path -quiet \
-from $req_clk \