From 7f72340be808e0498a3491e81154da721bad927c Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Fri, 26 Jul 2019 13:07:51 +0100 Subject: [PATCH] axi_dmac: fix timing constraints When source clock is asynchronous to request clock the rewind request handshake block must be constrained based on request clock domain. --- library/axi_dmac/axi_dmac_constr.ttcl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/library/axi_dmac/axi_dmac_constr.ttcl b/library/axi_dmac/axi_dmac_constr.ttcl index f947fe187..96c7492f5 100644 --- a/library/axi_dmac/axi_dmac_constr.ttcl +++ b/library/axi_dmac/axi_dmac_constr.ttcl @@ -67,16 +67,16 @@ set_max_delay -quiet -datapath_only \ [get_property -min PERIOD $src_clk] set_max_delay -quiet -datapath_only \ - -from $dest_clk \ + -from $req_clk \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ -filter {NAME =~ *i_rewind_req_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \ - [get_property -min PERIOD $dest_clk] + [get_property -min PERIOD $req_clk] set_max_delay -quiet -datapath_only \ -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ -filter {NAME =~ *i_rewind_req_fifo* && IS_SEQUENTIAL}] \ - -to $dest_clk \ - [get_property -min PERIOD $dest_clk] + -to $req_clk \ + [get_property -min PERIOD $req_clk] set_false_path -quiet \ -from $req_clk \